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J-GLOBAL ID：201401004158283445   Update date: Oct. 07, 2024

Ishihara Tohru

イシハラ トオル | Ishihara Tohru
Affiliation and department：
Nagoya University

About Nagoya University


Research field  (1)： Computer systems
Research theme for competitive and other funds  (14)：
  • 2024 - 2029 Highly Energy Efficient and Broadband Information Processing Platform based on Optical Functional Circuits
  • 2020 - 2023 光と電子が密に融合する集積回路のアーキテクチャと設計技術
  • 2017 - 2020 A Study on Optical Computer Design through Photonics and Electronics Co-Optimization
  • 2017 - 2020 Research on computing infrastructure aimed at realizing an IoT society to come
  • 2016 - 2020 LSI Design Method for Minimum Energy Operation
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Papers (158)：
  • Takumi KOMORI, Yutaka MASUDA, Tohru ISHIHARA. Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2024. E107.A. 1. 3-15
  • T. -F. Chen, Y. Masuda, T. Ishihara. A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. Proc. 36th IEEE International System-On-Chip Conference (SOCC). 2023
  • Jun Shiomi, Shogo Terada, Tohru Ishihara, Hidetoshi Onodera. Zero-Aware Fine-Grained Power Gating for Standard-Cell Memories in Voltage-Scaled Circuits. SOCC. 2022. 1-6
  • Takumi Komori, Yutaka Masuda, Tohru Ishihara. DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. RTCSA. 2022. 128-137
  • Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi. Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. DAC. 2022. 1285-1290
ｍore...
MISC (104)：
  • 陸佳萱, 増田豊, 石原亨. 近似コンピューティング回路の設計最適化に向けた計算重要度評価技術. 情報処理学会研究報告(Web). 2021. 2021. SLDM-195
  • 熊谷僚太, 増田豊, 石原亨. ファジングと高位合成を用いた近似コンピューティング回路のタイミング検証手法. 情報処理学会研究報告(Web). 2021. 2021. SLDM-195
  • 本多佑成, 増田豊, 石原亨. 近似コンピューティング回路の品質検証を高速化するファジングテスト法. 情報処理学会研究報告(Web). 2021. 2021. SLDM-195
  • 小森工, 増田豊, 塩見準, 石原亨. Approximate Minimum Energy Point Tracking Which Guarantees Real-Time Responses of Tasks. 回路とシステムワークショップ論文集(CD-ROM). 2021. 34th
  • 富山 葉月, 増田 豊, 石原 亨. 遅延故障に起因する回路寿命分布の確率的高速推定手法-Stochastic fast estimation of timing error induced circuit lifetime distribution-VLSI設計技術. 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報. 2020. 119. 443. 113-118
ｍore...
Patents (11)：
  • Optical Logic Circuit
  • 光乗算器および光乗算方法
  • 光論理回路
  • Optical Functional Unit
  • 光論理回路および加算器
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Books (3)：
  • Multi-Processor System-on-Chip 1
    Wiley - ISTE 2021
  • CMOS VLSI Design - A Circuits and Systems Perspective 4th ed.
    2014
  • Essential Issues in SOC Design: Designing Complex Systems-on-Chip
    Springer 2006
Lectures and oral presentations  (10)：
  • Near-Threshold Cache Architecture for Ultra-Low Energy Computing
    (2019)
  • Minimum Energy Point Tracking Exploiting All-Digital On-Chip Sensors
    (2018)
  • Minimum Energy Point Tracking for Self-Power IoT Processors
    (2017)
  • Minimum Energy Point Tracking under a Wide Range of PVT Conditions
    (The 20th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2016) 2016)
  • An Integrated Optical Parallel Adder: A First Step towards Light-Speed Data Path Operation
    (International Forum on MPSoC for Software-defined Hardware 2016)
ｍore...
Education (3)：
  • 1997 - 2000 Kyushu University
  • 1995 - 1997 Kyushu University
  • 1991 - 1995 Kyushu University School of Engineering
Professional career (1)：
  • 博士(工学) (九州大学)
Work history (7)：
  • 2018/10 - 現在 Nagoya University Graduate School of Informatics Professor
  • 2011/04 - 2018/09 Kyoto University Graduate School of Informatics Associate Professor
  • 2007/04 - 2011/03 Kyushu University System LSI Research Center Associate Professor
  • 2005/08 - 2007/03 Kyushu University System LSI Research Center Associate Professor
  • 2003/04 - 2005/07 Fujitsu Laboratories of America, Inc. Member of Research Staff
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Awards (17)：
  • 2021/10 - Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) Outstanding Paper Award 【An Accuracy Reconfigurable Multiply-Accumulate Unit Based on Operand-Decomposed Mitchell’s Multiplier】
  • 2021/05 - 電子情報通信学会 論文賞 【Methods for Reducing Power and Area of BDD-Based Optical Logic Circuits】
  • 2018/05 - 電子情報通信学会 論文賞 【Analytical Stability Modeling for CMOS Latches in Low Voltage Operation】
  • 2016/09 - IEEE International System on Chip Conference (SOCC) Best Paper Award 【Minimum Energy Poing Tracking Using Combined Dynamic Voltage Scaling and Adative Body Biasing】
  • 2016/09 - 情報処理学会システムLSI設計技術研究会 優秀論文賞 【CMOS LSIにおけるエネルギー最小点追跡のための電源電圧としきい値電圧の動的調節指針】
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