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J-GLOBAL ID:201601010643611561   Update date: Jul. 17, 2024

TAKAMAEDA Shinya

タカマエダ シンヤ | TAKAMAEDA Shinya
Affiliation and department:
Job title: Associate Professor
Homepage URL  (1): https://sites.google.com/site/shinyaty/
Research field  (1): Computer systems
Research keywords  (6): Neural Network ,  High Level Synthesis ,  Machine Learning ,  FPGA ,  Reconfigurable System ,  Computer Architecture
Research theme for competitive and other funds  (8):
  • 2023 - 2028 ゆらぎの熱力学に基づく確率的コンピューティング基盤の創出
  • 2021 - 2027 D3-AI: 多様性と環境変化に寄り添う分散機械学習基盤の創出
  • 2019 - 2023 性能最適化が容易なマルチパラダイム型高位合成フレームワークの創出
  • 2018 - 2023 Innovative Self-Learnable Architecture Platform for Accelerating Intelligent Computing
  • 2018 - 2022 アーキテクチャとアルゴリズムの協調による高効率深層学習システムの創出
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Papers (46):
  • Ou Y., Ambalathankandy P., Ikebe M., Takamaeda-Yamazaki S., Motomura M., Asai T. Real-time tone mapping: a survey and cross-implementation hardware benchmark. IEEE Transactions on Circuits and Systems for Video Technology. 2022. 32. 5. 2666-2686
  • Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Jaehoon Yu, Masato Motomura. Selective Fine-Tuning on a Classifier Ensemble: Realizing Adaptive Neural Networks with a Diversified Multi-Exit Architecture. IEEE Access. 2021. 9. 6179-6187
  • Hirayama Y., Asai T., Motomura M., Takamaeda-Yamazaki S. A hardware-efficient weight sampling circuit for Bayesian neural networks. International Journal of Networking and Computing. 2020. 10. 2. 84-93
  • Kota Shiba, Tatsuo Omori, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Masato Motomura, Mototsugu Hamada, Tadahiro Kuroda. A 3D-stacked SRAM using inductive coupling with low-voltage transmitter and 12:1 serdes. Proceedings - IEEE International Symposium on Circuits and Systems. 2020. 2020-
  • Kasho Yamamoto, Kazushi Kawamura, Kota Ando, Normann Mertig, Takashi Takemoto, Masanao Yamaoka, Hiroshi Teramoto, Akira Sakai, Shinya Takamaeda-Yamazaki, Masato Motomura. STATICA: A 512-Spin 0.25M-Weight Annealing Processor With an All-Spin-Updates-at-Once Architecture for Combinatorial Optimization With Complete Spin-Spin Interactions. IEEE Journal of Solid-State Circuits. 2020. 56. 1. 1-1
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MISC (35):
  • 安藤洸太, 植吉晃大, 大羽由華, 廣瀬一俊, 工藤巧, 池辺将之, 浅井哲也, 高前田伸也, 本村真人. Dither NN:画像処理から着想を得た組込み向け量子化ニューラルネットワークの精度向上手法. 電子情報通信学会技術研究報告. 2019. 119. 18(RECONF2019 1-19)(Web)
  • 池上高広, 池辺将之, 高前田伸也, 本村真人, 浅井哲也. An electronic circuit model for an early auditory system based on vestibulo-ocular reflex. 電子情報通信学会技術研究報告. 2018. 118. 173(ICD2018 14-38)
  • 工藤巧, 植吉晃大, 安藤洸太, 植松瞭太, 廣瀬一俊, 池辺将之, 浅井哲也, 本村真人, 高前田伸也. 対数量子化を用いた可変長ビットシリアル型DNNアクセラレータの面積最適化手法. 電子情報通信学会技術研究報告. 2018. 118. 63(RECONF2018 1-18)(Web)
  • 大羽由華, 安藤洸太, 廣瀬一俊, 植吉晃大, 植松瞭太, 工藤巧, 黒川圭一, 池辺将之, 浅井哲也, 本村真人, et al. 二値化ニューラルネットワークに基づいたハードウェア指向高精度モデルの検討. 電子情報通信学会技術研究報告. 2018. 118. 63(RECONF2018 1-18)(Web)
  • 熊澤輝顕, 鈴木浩史, 石畠正和, 浅井哲也, 池辺将之, 本村真人, 高前田伸也. ZDDを用いた三角形分割パターンの列挙とその応用に向けて. 人工知能学会人工知能基本問題研究会資料. 2018. 106th
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Education (4):
  • 2011 - 2014 Tokyo Institute of Technology Graduate School of Information Science and Engineering Department of Computer Science
  • 2009 - 2011 Tokyo Institute of Technology Graduate School of Information Science and Engineering Department of Computer Science
  • 2007 - 2009 Tokyo Institute of Technology School of Engineering Department of Computer Science
  • 2002 - 2007 National Institute of Technology, Fukushima College Department of Electrical Engineering
Professional career (1):
  • Doctor of Engineering (Tokyo Institute of Technology)
Work history (7):
  • 2019/10 - 現在 The University of Tokyo Department of Computer Science, Graduate School of Information Science and Technology Associate Professor
  • 2018/10 - 2022/03 Japan Science and Technology Agency PRESTO Researcher
  • 2019/04 - 2019/09 Hokkaido University Division of Electronics for Informatics, Faculty of Information Science and Technology Associate Professor
  • 2016/12 - 2019/09 Hokkaido University Research Center of Mathematics for Social Creativity, Research Institute for Electronic Science Associate Professor (Additional Post)
  • 2016/10 - 2019/03 Hokkaido University Division of Electronics for Informatics, Graduate School of Information Science and Technology Associate Professor
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