Rchr
J-GLOBAL ID:202101017628567704   Update date: May. 24, 2024

Yoshioka Kentaro

ヨシオカ ケンタロウ | Yoshioka Kentaro
Affiliation and department:
Homepage URL  (1): https://sites.google.com/keio.jp/keio-csg/
Research theme for competitive and other funds  (5):
  • 2023 - 2028 ゆらぎの熱力学に基づく確率的コンピューティング基盤の創出
  • 2023 - 2028 AI駆動型サイバーフィジカルシステムのセキュリティ評価・対策基盤
  • 2021 - 2026 D3-AI: 多様性と環境変化に寄り添う分散機械学習基盤の創出
  • 2022 - 2025 サイバーとフィジカルを横断したセンサセキュリティ研究
  • 2021 - 2023 LiDAR based Sensing System Focused on Privacy Preserving and Occlusions
Papers (40):
  • Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro. A 4.6-400 K Functional Ringamp-Based 250 MS/s 12 b Pipelined ADC With PVT-Robust Unity-Gain-Frequency-Aware Bias Calibration. IEEE J. Solid State Circuits. 2024. 59. 3. 740-752
  • Kentaro Yoshioka. 34.5 A 818-4094TOPS/W Capacitor-Reconfigured CIM Macro for Unified Acceleration of CNNs and Transformers. ISSCC. 2024. 574-576
  • Takami Sato, Yuki Hayakawa, Ryo Suzuki, Yohsuke Shiiki, Kentaro Yoshioka, Qi Alfred Chen. Revisiting LiDAR Spoofing Attack Capabilities against Object Detection: Improvements, Measurement, and New Attack. CoRR. 2023. abs/2303.10555
  • Kaoru Yamashita, Benjamin P. Hershberg, Kentaro Yoshioka, Hiroki Ishikuro. A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration. CICC. 2023. 1-2
  • Kentaro Yoshioka. A Tutorial and Review of Automobile Direct ToF LiDAR SoCs: Evolution of Next-Generation LiDARs. IEICE Transactions on Electronics. 2022. 105-C. 10. 534-543
more...
MISC (3):
  • Kentaro Yoshioka. An 818-TOPS/W CSNR-31dB SQNR-45dB 10-bit Capacitor-Reconfiguring Computing-in-Memory Macro with Software-Analog Co-Design for Transformers. CoRR. 2023. abs/2302.06463
  • Kentaro Yoshioka, Hidenori Okuni, Tuan Thanh Ta, Akihide Sai. Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections. IROS. 2021. 1578-1584
  • SEKIMOTO Ryota, SHIKATA Akira, YOSHIOKA Kentaro, KURODA Tadahiro, ISHIKURO Hiroki. A 40nm Ultra Low Voltage SAR ADC with Timing Optimized Asynchronous Clock Generator. Technical report of IEICE. SDM. 2012. 112. 169. 139-144
Patents (31):
Work history (3):
  • 2021/04 - 現在 Keio University Assistant Professor
  • 2014/04 - 2021/03 株式会社 東芝 研究員
  • 2017/12 - 2018/12 Stanford University Visiting Scholar
Committee career (3):
  • 2023/09 - 現在 Symposium on Vehicle Security and Privacy (VehicleSec) TPC Member
  • 2021/07 - 現在 IEEE VLSI Symposia Short Course Chair
  • 2020/07 - 現在 IEEE VLSI Symposia Technical Program Committee
Awards (5):
  • 2023/04 - IEEE CICC Outstanding Student Award A 4.6K to 400K Functional PVT-Robust Ringamp-Based 250MS/s 12b Pipelined ADC with Pole-Aware Bias Calibration
  • 2023/02 - Vehicle Sec ETAS Best Short/WIP Paper Award Runner-up WIP: Practical Removal Attacks on LiDAR-based Object Detection in Autonomous Driving
  • 2020/07 - Kaggle Prostate cANcer graDe Assessment (PANDA) Challenge 1st place
  • 2013/10 - IEEE A-SSCC Best Design Award A 40nm CMOS full asynchronous nano-watt SAR ADC with 98% leakage power reduction by boosted self power gating
  • 2013/01 - IEEE ASP-DAC Special Feature Award A 0.35-0.8V 8b 0.5-35MS/s 2bit/step extremely-low power SAR ADC.
Association Membership(s) (1):
IEEE
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