Rchr
J-GLOBAL ID:200901014310093172   Update date: Jan. 30, 2024

Takagi Kazuyoshi

タカギ カズヨシ | Takagi Kazuyoshi
Affiliation and department:
Job title: Professor
Homepage URL  (1): http://www.arch.info.mie-u.ac.jp/
Research field  (4): Electronic devices and equipment ,  Information networks ,  Computer systems ,  Information theory
Research keywords  (6): 超伝導ディジタル回路 ,  論理設計支援 ,  論理回路設計 ,  Superconductive Digital Circuits ,  Computer-Aided Logic Design ,  Logic Circuit Design
Research theme for competitive and other funds  (24):
  • 2018 - 2021 Researches on Testing and Reliable Design of Superconducting Rapid Single-Flux-Quantum Circuits
  • 2016 - 2020 Studies on hardware assist of floating point function calculation
  • 2015 - 2018 Studies on Layout Design Methods for Logic Circuits using Superconducting Devices
  • 2012 - 2015 studies on high-reliability timing design methods for logic circuits using advanced devices
  • 2012 - 2015 Research on high-performance and highly-dependable floating-point arithmetic unit arrays by contriving data representation
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Papers (100):
  • Nobutaka Kito, Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi. Technology Mapping With Clockless Gates for Logic Stage Reduction of RSFQ Logic Circuits. IEEE Transactions on Applied Superconductivity. 2023. 33. 5. 1-5
  • Masamitsu Tanaka, Ryo Sato, Akira Fujimaki, Kazuyoshi Takagi, Naofumi Takagi. Execution of stored programs by a rapid single-flux-quantum random-access-memory-embedded bit-serial microprocessor using 50-GHz clock frequency. Applied Physics Letters. 2023. 122. 19
  • Takahiro Kawaguchi, Kazuyoshi Takagi, Naofumi Takagi. Static Timing Analysis for Single-Flux-Quantum Circuits Composed of Various Gates. IEEE Transactions on Applied Superconductivity. 2022. 32. 5. 1-9
  • Nobutaka Kito, Kazuyoshi Takagi, Naofumi Takagi. Logic-Depth-Aware Technology Mapping Method for RSFQ Logic Circuits With Special RSFQ Gates. IEEE Transactions on Applied Superconductivity. 2022. 32. 4. 1-5
  • Nobutaka Kito, Kazuyoshi Takagi. An RSFQ flexible-precision multiplier utilizing bit-level processing. Journal of Physics: Conference Series. 2021. 1975. 1
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MISC (315):
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Works (9):
  • 単一磁束量子回路による再構成可能な低電力高性能プロセッサ
    2006 - 2011
  • テスト容易な演算回路の自動合成に関する研究
    2008 - 2010
  • 局在電磁波配線を用いた単一磁束量子論理回路の設計および設計支援に関する研究
    2006 - 2009
  • 次世代集積回路設計のための決定グラフによる論理関数表現に関する研究
    2005 - 2007
  • ハードウェアアルゴリズムの性能評価に関する研究
    2004 - 2007
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Education (6):
  • - 1995 Kyoto University
  • - 1995 Kyoto University Graduate School, Division of Engineering Department of Information Science
  • - 1993 Kyoto University
  • - 1993 Kyoto University Graduate School, Division of Engineering Department of Information Science
  • - 1991 Kyoto University Faculty of Engineering
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Professional career (2):
  • Master of Engineering (Kyoto University)
  • Doctor of Engineering (Kyoto University)
Work history (10):
  • 2019/04 - 現在 Mie University Dept. Information Engineering, G.S. Information Engineering Professor
  • 2011/04 - 2019/03 Kyoto University Dept. Communications and Computer Engineering, G.S. Informatics Associate Professor
  • 2007/04 - 2018/03 The University of Tokyo VDEC Cooperative Researcher
  • 2007/04 - 2011/03 Nagoya University Dept. Information Engineering, G.S. Information Science Associate Professor
  • 2006/07 - 2007/03 Nagoya University Dept. Information Engineering, G.S. Information Science Associate Professor
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Association Membership(s) (5):
LAシンポジウム ,  情報処理学会 ,  電子情報通信学会 ,  IEEE ,  IEEE
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