Rchr
J-GLOBAL ID：200901015971474624
Update date: Sep. 27, 2024
Hanyu Takahiro
ハニュウ タカヒロ | Hanyu Takahiro
Affiliation and department：
Job title：
Professor
Homepage URL (2)：
https://www.riec.tohoku.ac.jp/ja/organization/section4/vlsi/
,
https://www.riec.tohoku.ac.jp/en/organization/section4/vlsi/
Research field (3)：
Computational science
, Soft computing
, Computer systems
Research keywords (3)：
Device-model-based electronics
, New Paradigm VLSI
, Nonvolatile Logic-in-Memory Architecture
Research theme for competitive and other funds (30)：
- 1986 - 現在 Device-Model-Based Electronics
- 1986 - 現在 Nonvolatile Logic-in-Memory VLSI Technology
- 1983 - 現在 Multiple-Valued Integrated Systems
- 2021 - 2025 Development of a high-speed and ultra-low-power die-hard logic LSI fundamental technology for IoT applications
- 2021 - 2025 確率的デバイスモデルに基づく量子モンテカルロ計算ハードウェアプラットフォーム構築
- 2021 - 2025 スピントロニクスベース高性能・省電力・高信頼IoTセンサノードの基盤研究開発
- 2016 - 2021 脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発
- 2015 - 2018 Study on Implementation for Greatly Reducing Power Dissipation of Serial Communication Mechanisms
- 2016 - 2017 脳型コンピューティング向けダーク・シリコンロジックLSIの基盤技術開発
- 2010 - 2014 Nonvolatile-device-based PVT-variation-resilient VLSI system
- 2006 - 2008 Implementation of a High-Speed LDPC Decoder LSI Based on a Multiple-Valued Full-Duplex Data-Transfer Technique
- 2006 - 2007 不揮発性デバイスに基づくクイックオンVLSIシステムの構成
- 2003 - 2005 Implementation of a High-Speed Asynchronous Data Transfer VLSI Based on Bidirectional Current-Mode Multiple-Valued Circuit Techniques
- 2001 - 2004 Implementation of a Transfer-Bottleneck-Free Multiple-Valued Logic-in-Memory VLSI and Its Application
- 2002 - 2002 多値技術に基づく高速データ転送とそのマルチメディアVLSIプロセッサへの応用
- 2000 - 2002 Implementation of a High-Performance Multiple-Valued Current-Mode VLSI System with Low-Power and Highly Reliable Capabilities
- 2000 - 2002 Interconnection-Bottleneck-Free VLSI System Based on Dual-Rail Multiple-Valued Digital Computing
- 1997 - 2000 Implementation of a One-Transistor Multiple-Valued Content-Addressalbe Memory and Its Application
- 1998 - 1999 高速・低電力電流モード多値算術演算VLSI回路の試作
- 1997 - 1999 Development of a Chip Family for Ultra-Highly-Parallel Multiple-Valued Integrated Circuits and Its Applications
- 1997 - 1999 High-Level Synthesis of High-Performance VLSI Processors for Intelligent Integrated System
- 1997 - 1998 MULTIPLE-VALUED PROCESSOR FOR INTELLIGENT INTEGRATED SYSTEM
- 1996 - 1996 超並列多値連想メモリに関する研究
- 1995 - 1996 Study on Multiple-Valued VLSI Processors for a Highly Safe Intelligent Vehicle
- 1994 - 1996 Ultra-Highly-Parallel Arithmetic and Logic Circuits and Their Multiple-Valued Integration
- 1994 - 1994 次世代デバイスに基づく高性能多値VLSIシステムの構成に関する研究
- 1993 - 1993 ロボットビジョン用特徴抽出VLSIプロセッサシステムの構成に関する研究
- 1992 - 1993 Study on Post-Binary ULSI Sstems
- 1991 - 1992 IMPLEMENTATION OF ULTRA-HIGH-SPEED INFERENCE HARDWARE ENGINE BASED ON 4-VALUED CMOS INTEGRATED CIRCUITS AND ITS APPLICATION
- 1989 - 1991 BASIC STUDY ON HIGH-PERFORMANCE MULTIPLE-VALUED SUPER CHIP FOR INTELLIGENT ROBOTS
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Papers (539)：
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Naoya Onizawa, Takahiro Hanyu. Enhanced convergence in p-bit based simulated annealing with partial deactivation for large-scale combinatorial optimization problems. Scientific Reports. 2024. 14. 1
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Naoya Onizawa, Ryoma Sasaki, Duckgyu Shin, Warren J. Gross, Takahiro Hanyu. Stochastic Simulated Quantum Annealing for Fast Solution of Combinatorial Optimization Problems. IEEE Access. 2024. 12. 102050-102060
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Taiga Kubuta, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu. Stochastic Implementation of Simulated Quantum Annealing on PYNQ. 2023 International Conference on Field Programmable Technology (ICFPT). 2023
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Ken Asano, Masanori Natsui, Takahiro Hanyu. Error-Sensitivity-Aware Write-Energy Optimization for an MTJ-Based Binarized Neural Network. 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS). 2023
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Ryoma Sasaki, Duckgyu Shin, Naoya Onizawa, Takahiro Hanyu. Improving Stochastic Quantum-Like Annealing Based on Rerandomization. 2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS). 2023
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MISC (131)：
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Daisuke Suzuki, Takahiro Hanyu. Nonvolatile field-programmable gate array using a standard-cell-based design flow. IEICE Transactions on Information and Systems. 2021. E104D. 8. 1111-1120
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夏井雅典, 羽生貴弘. New-Paradigm Logic-LSI Design Technology Based on Nonvolatile Storage Functionality and Its Future Prospects. 電子情報通信学会論文誌 C(Web). 2021. J104-C. 6
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坂本佳介, 夏井雅典, 羽生貴弘. パワーゲーティング機能付き不揮発RISC-V CPUの基礎検討. 電気関係学会東北支部連合大会講演論文集(CD-ROM). 2021. 2021
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ZHONG Fangcen, ZHONG Fangcen, 夏井雅典, 羽生貴弘. Operating-Condition-Aware Power-Gating-Switch Control Technique and Its Application to Nonvolatile Logic LSI. 電子情報通信学会技術研究報告(Web). 2021. 121. 277(VLD2021 17-48)
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ZHONG Fangcen, 夏井雅典, 羽生貴弘. Power-Gating Switch-Control Technique for Nonvolatile Logic LSI. 電子情報通信学会技術研究報告(Web). 2020. 120. 234(VLD2020 11-38)
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Patents (7)：
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完全二重非同期通信システム
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磁気抵抗効果素子を用いたロジックインメモリ回路
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論理演算回路,論理演算装置および論理演算方法
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論理演算回路および論理演算方法
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論理演算回路および論理演算方法
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Books (4)：
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Introduction to Magnetic Random-Access Memory
Wiley-IEEE Press 2016 ISBN:9781119009740
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Spintronics-based Computing
Springer 2015 ISBN:9783319151793
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VLSI 2010 Annual Symposium: Selected Papers (Lecture Notes in Electrical Engineering)
Springer-Verlag 2011 ISBN:9400714874
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半導体ストレージ2012
日経BP社 2011 ISBN:9784822265588
Lectures and oral presentations (99)：
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不揮発FPGAを用いた脳型情報処理アクセラレータの構成
(信学会第2種研究会「多値論理とその応用」 2018)
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脳型計算に基づく非シグネチャ不正侵入検出手法
(信学会第2種研究会「多値論理とその応用」 2018)
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複数個の電圧電流変換特性を用いた低電力MTJベース真性乱数生成器の設計
(信学会第2種研究会「多値論理とその応用」 2018)
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Contextual Cueing Model に基づく実時間画像認識プリプロセッサの検討
(信学会第2種研究会「多値論理とその応用」 2018)
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時系列特徴を用いたチップ内データ転送エラー訂正手法とその可能性
(デザインガイア2017 2017)
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Professional career (1)：
- Ph. D (Tohoku University)
Awards (15)：
- 2018/05 - Technical Committee on Integrated Circuits and Devices (ICD), IEICE Excellent Young Researcher Presentation Award
- 2015/04 - MEXT The Commendation for Science and Technology "Study of Nonvolatile Logic-in-Memory Integrated Circuits"
- 2014/05 - IEEE ASYNC 2014 Best Paper Award Finalist "A Compact Soft-Error Tolerant Asynchronous TCAM Based on a Transistor/Magnetic-Tunnel-Junction Hybrid Dual-Rail Word Structure"
- 2012/09 - SSDM 2012 Paper Award "High-Density and Low-Power Nonvolatile Static Random Access Memory Using Spin-Transfer-Torque Magnetic Tunnel Junction"
- 2010/07 - IEEE ISVLSI 2010 Best Paper Award "Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model"
- 2010/05 - The Institute of Electronics, Information and Communication Engineers Excellent Paper Award "Design of a Lookup Table Circuit Based on TMR Logic and Its Application to an Immediate Wake-Upable FPGA"
- 2010/04 - Ichimura Academic Award "Development of Nonvolatile Logic-in-Memory Integrated Circuits"
- 2009/09 - The Japan Society of Applied Physics Excellent Paper Award (JJAP Paper Award) "Standby-Power-Free Compact Ternary Content-Addressable Memory Cell Chip Using Magnetic Tunnel Junction Devices"
- 2007/01 - ASP-DAC 2007 University LSI Design Contest Special Feature Award "Implementation of a Standby-Power-Free CAM Based on Complementary Ferroelectric-Capacitor Logic"
- 2002/11 - 2002年システムLSIワークショップ 優秀ポスター賞 "Design of Low-Power Logic-in-Memory VLSI Using Ferroelectric Devices"
- 2002/06 - 2002年度(第9回)LSIデザイン・オブ・ザ・イヤー 審査員特別賞 強誘電体デバイスを用いたシステムLSI構築技術
- 2000/05 - (社)情報処理学会 坂井記念特別賞 "Multiple-Valued Logic-in-Memory VLSI Based on Floating-Gate MOS Pass-Transistor Logic"
- 1988/05 - IEEE ISMVL Distinctive Contribution Award "Quaternary Gate Array for Pattern Matching and its Application to Knowledge Information Processing System"
- 1988/02 - 丹羽記念会 丹羽記念賞 "Design and Implementation of an nMOS Image Processor Based on Quaternary Logic"
- 1986/05 - IEEE ISMVL Award for Excellence "Implementation of Quaternary NMOS Integrated Circuits for Pipelined Image Processing"
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Association Membership(s) (4)：
The Japan Society of Applied Physics
, Information Processing Society of Japan
, The Institute of Electronics, Information and Communication Engineers
, 米国電気電子工学会(The Institute of Electrical and Electronics Engineers)
