- 2020 - 2023 Minimization of variables for classification functions, and its applications.
- 2017 - 2020 インデックス生成関数の分解に関する研究
- 2014 - 2018 High-speed pattern matching
- 2011 - 2014 Logic synthesis using linear transformation and memories.
- 2007 - 2009 A study on the realization and application of content-addressable memory using general-purpose memory
- 2004 - 2005 ルック・アップ・テーブル・リングの論理合成
- 2002 - 2004 Research on programmable logic elements using the virtual wiring and their logic synthesis method
- 2000 - 2002 Development of hardware logic simulator using decision diagrams
- 1999 - 2001 Studies on logic design and testing methodology for very high performance VLSIs
- 1998 - 2000 Decomposition of Large-Scale Logic Functions
- 1996 - 1997 A Research on the realization of three-level logic networks
- 1993 - 1995 A Research on the development of a logic synthesis system using EXOR gates
- 1993 - 1994 A Research on the Representation and Manipulation of Logical Expressions using Ternary Decision Diagrams
- 1992 - 1993 Study on Post-Binary ULSI Sstems
- 1990 - 1992 Development of A Silicon Complilation System for Rewritable LSIs
- 1990 - 1991 Logic synthesis using EXOR gates
- 1988 - 1990 Data-Driven Ultra-Parallel Processing Scheme Based on "Flow-Thru Processing" Concept
- 1988 - 1989 Decomposition of large-scale Programmable logic arrays
- 1986 - 1988 User-language processing system based on diagrammatical representations
- 1986 - 1987 ULSI-oriented data-driven highly-parallel processing scheme based on diagrammatical languwges
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