Rchr
J-GLOBAL ID:200901020677380585   Update date: Nov. 25, 2019

Yamashita Shigeru

ヤマシタ シゲル | Yamashita Shigeru
Affiliation and department:
Job title: Professor
Other affiliations (2):
Homepage URL  (1): http://www.ngc.is.ritsumei.ac.jp/~ger/
Research field  (3): High-performance computing ,  Computer systems ,  Information theory
Research keywords  (1): Dependable Computing, Low Power, Logic Circuit Design, Reversible Logic Synthesis, GPGPU, Reconfigurable Computing, Quantum Computing, Biochip Design
Papers (68):
  • Wakaki Hattori, Shigeru Yamashita. Mapping to 2D Nearest Neighbor Architecture by Changing the Gate Order. IEICE Transactions on Information and Systems. 2019. Vol.E102-D. 11. To apear
  • C. Liu, C. Lin, Y. Chen, C. Wu, C. Wang, S. Yamashita. Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments. IEEE Trans. CAD. 2019. PP. 1-1
  • 梅田悠人, 山下茂. 整数計画ソルバーを用いたNetworked Labs-on-Chipの設計手法. 電子情報通信学会論文誌 D. 2019. Vol.J102-D. 6. 423-433,
  • 浅井孝太, 星孝太郎, 山下茂. 大規模TQEC回路の自動最適化手法. 電子情報通信学会論文誌 D. 2019. Vol.J102-D. 5. 367-377
  • Kota Asahi, Shigeru Yamashita. Compaction of Topological Quantum Circuits by Modularization. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. 2019. Vol.E102-A. 4. 624-632
more...
Books (6):
  • 量子コンピュータ/イジング型コンピュータ研究開発最前線
    情報機構 2019
  • 電子情報通信学会 100年史
    電子情報通信学会 2017
  • OHM大学テキスト コンピュータアーキテクチャ
    オーム社 2012
  • 知識ベース 6群 2編 6章 6-4 量子計算の節
    電子情報通信学会 2011
  • 第2版現代数理科学辞典
    丸善株式会社 2009
more...
Lectures and oral presentations  (191):
  • An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid
    (pp. 162-168 In: Thomsen M., Soeken M. (eds) Reversible Computation. RC 2019. Lecture Notes in Computer Science, vol 11497, 2019. 2019)
  • Reactant Minimization for Multi-Target Sample Preparation on Digital Microfluidic qq Biochips using Network Flow Models
    (Proc. of International Symposium on VLSI Design, Automation & Test (VLSI-DAT), D6-1, Apr. 2019 (Best Paper Candidate) 2019)
  • Reducing the Overhead of Stochastic Number Generators Without Increasing Error
    (in the Proceedings of 32th International Conference on VLSI Design, pp. 52-57, Jan. 2019 2019)
  • NLoCの自動設計手法と最適な構造の提案
    (電子情報通信学会技術研究報告, VLD2018-40 2018)
  • 演算誤差と回路面積のトレードオフを考慮したStochastic Numberの生成手法,
    (電子情報通信学会技術研究報告, VLD2018-47 2018)
more...
Education (2):
  • - 1995 Kyoto University "Graduate School, Division of Engineering" Information Science
  • - 1993 Kyoto University Faculty of Engineering Department of Information Science
Professional career (1):
  • Ph.D. in information science (Kyoto University)
Work history (3):
  • 2012/04/01 - Visiting Professor, National Institute of Informatics
  • 2009/04 - Ritsumeikan University
  • 2003/04 - 2009/03 Nara Institute of Science and Technology
Committee career (50):
  • 2018/04 - 2020/03 Information Processing Society of Japan Information Processing Society of Japan Kansai Branch Executive Secretary
  • 2018/04 - 2020/03 Information Processing Society of Japa Information Processing Society of Japan Kansai Branch Executive Secretary
  • 2017/01 - 2019/01 IEEE Computer Society Kansai Chapter Chair
  • 2009 - 2019 電子情報通信学会論文誌「VLSI Design and CAD Algorithms小特集」編集委員(2009-2019)
  • 2019 - IEEE International Symposium on VLSI Design and Test TPC Member 2019
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Awards (9):
  • 2018/03 - The 16th Workshop on Synthesis And System Integration of Mixed Information technologies Best Paper Award
  • 2014/01 - ASP-DAC ASP-DAC 2014 Best Paper Candidate
  • 2013 - IEEE IEEE Senior Member
  • 2011/03 - 2010 IPSJ Yamashita SIG Research Award
  • 2011/03 - Marubun Academic Achievement Award of the Marubun Research Promotion Foundation
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Association Membership(s) (4):
Association for Computing Machinery ,  The Institute of Electrical and Electronics Engineers (IEEE) ,  The Information Processing Society of Japan ,  The Institute of Electronics, Information and Communication Engineers (IEICE)
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