Fujimoto Kuniaki

フジモトクニアキ | Fujimoto Kuniaki

Affiliation and department：
Homepage URL (1)： http://www2.kuma.u-tokai.ac.jp/~kfuji/

Research field (2)： Electronic devices and equipment , Computer systems

Research keywords (11)：ニューロンCMOS , 連想メモリ , 自動診断 , メラノーマ , 悪性黒色腫 , ニューラルネットワーク , ディジタル回路 , パルス回路 , 電子回路 , 集積回路工学 , 知能情報処理

Research theme for competitive and other funds (3)：

2022 - 2025 A Study on a Low Power Variable Logic Circuit Using Neuron CMOS Inverters
2015 - 2018 Associative Memory Using Neuron CMOS Inverters
2012 - 2015 High-Speed and Low Power Consumption AD Converter Using Neuron MOSFET

Papers (114)：

西口大嗣, 矢原充敏, 原田裕二郎, 福原雅朗, 藤本邦昭. A Range Hamming Distance Search Associative Memory Based on Electronic Neurons Using Interconnect Capacitance. 電子情報通信学会論文誌 C(Web). 2024. J107-C. 4
西口大嗣, 矢原充敏, 原田裕二郎, 福原雅朗, 藤本邦昭. A Proposal of PLL Using Digital Controlled Oscillator Based on Multi-Phase Clock. 電子情報通信学会論文誌 C(Web). 2024. J107-C. 4
Daishi Nishiguchi, Yujiro Harada, Mitsutoshi Yahara, Kuniaki Fujimoto. A Study of High-Speed Hamming Distance Detection Circuit Utilizing a Neuron CMOS Inverter. International Journal of Electrical and Electronic Engineering and Telecommunications. 2024. 13. 3. 224-228
Daishi Nishiguchi, Mitsutoshi Yahara, Yujiro Harada, Masaaki Fukuhara, Kuniaki Fujimoto. DESIGN OF FREQUENCY MULTIPLIER BASED ON DOUBLE-EDGE COUNTER AND ITS ANALYSIS. ICIC Express Letters, Part B: Applications. 2024. 15. 1. 35-42
Yujiro Harada, Yoshiki Katoda, Masaki Fukuhara, Daishi Nishiguchi, Kuniaki Fujimoto. A STUDY OF A MINIMUM EUCLIDEAN DISTANCE SEARCH CIRCUIT FOR AN ASSOCIATIVE MEMORY. ICIC Express Letters. 2023. 17. 10. 1111-1118

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MISC (6)：

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Patents (4)：

Books (4)：

Lectures and oral presentations (16)：

Land Cover Change Detection before and after the 2016 Kumamoto Earthquake Using Remote Sensing
(Record of Joint Conference of Electrical and Electronics Engineers in Kyushu 2019)
A-1-22 A Study on Dividing Circuit with Multi-Phase Input Clocks
(Proceedings of the IEICE General Conference 2006)
A Study on Dividing Ratio Changeable m Multiplication Circuit with Delay Circuit.
(Record of Joint Conference of Electrical and Electronics Engineers in Kyushu 2005)
A-1-12 A Study on Analog Digital Mixed PLL
(Proceedings of the IEICE General Conference 2004)
Dividing Ratio Changeable All Digital Phase Locked Loop with Low Jitter
(Record of Joint Conference of Electrical and Electronics Engineers in Kyushu 2004)

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Education (2)：

1987 - 1989 Tokai University Graduate School of Engineering
1983 - 1987 Tokai University School of Engineering Department of Electrical and Electronic Engineering

Professional career (2)：

Work history (2)：

Committee career (3)：

Awards (10)：

2017/09 - 日本知能情報ファジィ学会貢献賞
2017/08 - Best Paper Award A Wide Range Manhattan Distance Search Circuit Using Neuron CMOS Inverters
2016/11 - バイオメディカル・ファジィ・システム学会貢献賞
2015/08 - Contribution Award
2015/08 - Excellent Paper Award A Minimum Manhattan Distance Retrieving Circuit Using Neuron CMOS Inverters

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Association Membership(s) (5)：

電子情報通信学会 , 九州工学教育協会 , 日本工学教育協会 , 電気学会 , 日本知能情報ファジィ学会

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