Rchr
J-GLOBAL ID：200901096830201420
Update date: Jan. 30, 2024
TSUTOMU YOSHIMURA
ヨシムラ ツトム | TSUTOMU YOSHIMURA
Affiliation and department：
Homepage URL (1)：
http://www.oit-tyoshimura.jpn.org/index.html
Research field (1)：
Electronic devices and equipment
Research keywords (2)：
集積回路
, アナログ電子回路
Research theme for competitive and other funds (6)：
Papers (4)：
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Mayu Kobayashi, Yuya Masui, Takao Kihara, Tsutomu Yoshimura. Spur reduction by self-injection loop in a fractional-N PLL. ICECS 2017 - 24th IEEE International Conference on Electronics, Circuits and Systems. 2018. 2018-. 260-263
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Kazuki Miyao, Tatsuya Okafuji, Takao Kihara, Tsutomu Yoshimura. Study of mutual injection pulling in a 5-GHz, 0.18-μm CMOS cascaded PLL. 2018 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2018, Chengdu, China, October 26-30, 2018. 2018. 175-178
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Naohiro Fujii, Shuei Morishita, Takao Kihara, Tsutomu Yoshimura. A 2.6GHz Subharmonically Injection-Locked PLL with Low-Spur and Wide-Lock-Range Injection. 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS). 2016
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Shuei Morishita, Shinji Shimizu, Takao Kihara, Tsutomu Yoshimura. Subharmonically Injection-Locked PLL with Variable Pulse-Width Injections. 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS). 2015. 557-560
MISC (15)：
Books (1)：
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デジタルシステム工学 応用編
丸善株式会社 2003
Education (2)：
- 2000 - 2005 Hiroshima University
- 1985 - 1991 The University of Tokyo Graduate School of Science
Professional career (1)：
Awards (2)：
- 2007 - IEEE Transactions on Circuits and Systems 2007 Darlington Best Paper Awards
- 2000 - One of the 100 Most Technologically Significant New Products of the Year (R&D 100)
Association Membership(s) (3)：
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