Takeuchi Yoshinori

Affiliation and department：
Job title： Associate Professor

Research field (4)： Computer systems , High-performance computing , Control and systems engineering , Communication and network engineering

Research keywords (7)： Computer Architecture , Embedded Systems , SoC Design , Design Automation , VLSI Design Methodology , VLSI Design , Signal Processing

Research theme for competitive and other funds (23)：

2020 - 2024 網膜と視覚野の情報処理と通信に学んだ脳刺激型人工視覚の開発
2017 - 2020 Study for Low Energy Information Sensing for IoT Devices
2016 - 2019 Hardware-oriented Algorithms and Implementation Methodology for Object Recognition
2014 - 2017 Higher Reliable Task Assignment Method for Embedded Multiprocessor
2013 - 2016 Research for Task assignment methods considering input data variability

Show all

Papers (253)：

吉澤翔悟, 武内良典. オペコードコンパクト化によるプロセッサの回路面積低減の評価. DAシンポジウム2023論文集. 2023. 2023. 71-77
田中尚哉, 平山聖冴, 武内良典. 人工視覚システムのデータ圧縮伸長モジュールのFPGA実装. 情報処理研究報告, SLDM-201. 2023. 2023. 97-102
平山聖冴, 田中尚哉, 武内良典. 視覚野刺激型人工視覚システムの刺激データに対する圧縮プロセッサ設計. 情報処理学会研究報告, SLDM-201. 2023. 2023. 90-96
上田匠, 武内良典. 視覚野刺激型人工視覚システムの重み付き刺激データ表現の符号化手法の提案. 2022年度情報処理学会関西支部支部大会、G23. 2022
津村直宏, 武内良典. ドーパミン変調 STDP を用いたスパイキングニューラルネットワークの学習評価. 2022年度情報処理学会関西支部支部大会、G09,. 2022

ｍore...

MISC (483)：

Proposal of a Bedtime ECG Measurement System for Detecting Heart Diseases. 2016. 115. 518. 217-222
TAKEUCHI YOSHINORI, YU JAEHOON, YAMANAKA TATSUYA, Khan Arif Ullah, SEKINE MASAKI, IMAI MASAHARU. Proposal of an Unconscious Bioelectric Potential Measurement System for Bedtime ECG Acquisition. IEICE technical report. Computer systems. 2015. 114. 506. 291-296
TAKEUCHI YOSHINORI, YU JAEHOON, YAMANAKA TATSUYA, Khan Arif Ullah, SEKINE MASAKI, IMAI MASAHARU. Proposal of an Unconscious Bioelectric Potential Measurement System for Bedtime ECG Acquisition. IEICE technical report. Dependable computing. 2015. 114. 507. 291-296
An Instruction-set Test Method for Compiler Generation of Application Specific Instruction-set Processors. 2014. 2014. 151-156
YAMASHITA Tomohiro, YU Jaehoon, TAKEUCHI Yoshinori, IMAI Masaharu. high speed super-resolution based on compressed sensing. Mathematical Systems Science and its Applications : IEICE technical report. 2014. 114. 125. 75-80

ｍore...

Patents (8)：

生体情報の圧縮方法およびデータ圧縮装置
電子トリアージシステム
VLIWプロセッサ自動生成方法及び自動生成プログラム
メモリアクセス制御装置及びATM制御装置メモリアクセス制御装置及びATM制御装置
「パイプライン回路合成方法

ｍore...

Books (7)：

論理回路
オーム社 2016 ISBN:9784274218064
"ASIP Meister,"Processor Description Languages,Prabhat Mishra and Nikil Dutt, eds.
Springer 2008
"Dynamic Reconfigurable Architecture Exploration based on Parameterized Reconfigurable Processor Model,"VLSI-SoC: Research Trends in VLSI and Systems on Chip,Giovanni De Micheli, Salvador Mir, Ricardo Reis, eds,
Springer 2007
System Level Synthesis
Kluwer Academic Publishers 1999
'Compiler Generation Techniques for Embedded Processors and thier Application to HW/SW Codesign' System Level Synthesis, (共著)
1999

ｍore...

Lectures and oral presentations (2)：

Challenges for Processor Instruction Extension in MPSoC Era
(19th International Forum on MPSoC for Software-defined Hardware 2019 (MPSoC 2019) 2019)
Coding Analysis for Spiking Neural Network Models
(18th International Forum on MPSoC for Software-defined Hardware 2018 2018)

Works (13)：

Optimization for Dynamic Reconfigurable Components
2008 -
災害時救命救急支援を目指した人間情報センシングシステムの開発
2008 -
医療用汎用SoCデバイスの開発
2008 -
マルチプロセッサSoCのアーキテクチャ設計最適化手法
2008 -
ダイナミック・リコンフィギャラブル・コンポーネントの設計最適化手法
2008 -

ｍore...

Education (4)：

- 1992 Tokyo Institute of Technology Graduate School, Division of Science and Engineering
- 1992 Tokyo Institute of Technology Science of Engineering
- 1987 Tokyo Institute of Technology Faculty of Engineering
- 1987 Tokyo Institute of Technology School of Engineering

Professional career (2)：

(BLANK) (Tokyo Institute of Technology)
(BLANK) (Tokyo Institute of Technology)

Work history (9)：

2018 - 現在 Kindai University Faculty of Science and Engineering
2007 - 2017 Osaka University Graduate School of Information Science and Technology
2002 - 2006 Osaka University Graduate School of Information Science and Technology
1999 - 2002 : 大阪大学大学院基礎工学研究科助教授
1997 - 1999 : 大阪大学大学院基礎工学研究科講師

Show all

Committee career (15)：

2023/06 - 現在 IPSJ Transactions on System LSI Design Methodology Associate Editors-in-Chief
2023/01 - 現在電子情報通信学会『Special Section on VLSI Design and CAD Algorithms』編集委員会編集委員
2022/11 - 現在電子情報通信学会『Special Section on Circuits and Systems』編集委員会編集委員
2014 - 現在情報処理学会「組込みシステム工学」特集号編集委員会編集委員
2021/06 - 2023/05 IPSJ Transactions on System LSI Design Methodology Associate Editor

Show all

Awards (8)：

2019 - IPSJ IPSJ Transactions on System LSI Design Methodology, Best Paper Award Parallelism-flexible Convolution Core for Sparse Convolutional Neural Networks on FPGA
2016 - 情報処理学会組込みシステム研究会優秀論文賞共有資源モデル記述を用いた実時間制御システムのモデリング手法
2011 - The Institute of Electronics Engineers of Korea The IEEK Semiconductor & Device Society paper award
2010 - IEEE Solid-State Circuits Society Japan Chapter Academic Research Award
2010 - IEEE Solid-State Circuits Society Japan Chapter IEEE Solid-State Circuits Society Japan Chapter Academic 0Research Award

Show all

Association Membership(s) (4)：

ACM , INFORMATION PROCESSING SOCIETY OF JAPAN , IEEE , THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS

※ Researcher’s information displayed in J-GLOBAL is based on the information registered in researchmap. For details, see here.

Return to Previous Page