Research field (2)：
Information networks
, Computer systems
Research keywords (5)：
FPGA development
, runtime optimization
, compiler optimization
, マルチスレッド化処理
, automatic multithreaded code transformation
Research theme for competitive and other funds (21)：
2017 - 2020 Large-Scale Pixel Computation for 3D Holographic Display with Fine Granularity and Wide View Angle
2015 - 2018 Research and development of fundamental technology to realize flexible parallel processing using mobile computing devices
2013 - 2017 Source-level parallelization system for CPU/GPU combined heterogeneous architecture
2012 - 2016 Study on Self-Lookahead Control Mechanisms in Large-Scale Interconnection Networks
2013 - 2015 A design method of distributed-parallel processing system for FPGAs based on process network
2012 - 2015 Research on high-performance path-base thread decomposition method based on global restruction of program codes
2009 - 2011 Dynamic Selection of Speculative Threads Based on Executed Loop Paths
2009 - 2011 Theoretical Foundation and its Engineering Application on Extra Large-Scale Interconnection Networks by Empirical Approach
2008 - 2010 Research on binary-level speculative multithreading for general-purpose multi-core processors
2007 - 2008 Establishment of Fundamental Technology for Global Optimization of Interconnection Networks for Huge-Scale Parallel Systems
2006 - 2008 High Performance Chip Multiprocessor with Self Optimization Capability Based on Frequently Executed Paths
2005 - 2007 バイナリレベル複数スレッド化のためのバイナリコード解析技術の研究開発
2004 - 2006 Study on Interconnection Networks that Employ Autonomous Optimization Functions based on Global Behavior Understanding
2002 - 2005 High-Performance Multicomputer based on Receiving Message Prediction
2002 - 2004 バイナリレベル複数スレッド化による計算機の高速化に関する研究
2002 - 2003 Study on Global Optimization Method of Interconnection Networks using Autonomous Operations
2002 - バイナリ変換処理によるプログラムコードの自動マルチスレッド化処理
2002 - binary level multithreading
2000 - 2001 Receiving Message Prediction and Speculative Execution of the Receiving Process
1998 - 2000 Design and Implementation of the A-NET Multicomputer based on System-on-Chip Architecture
1997 - 1998 High Performance Implementation of a Parallel Object-Oriented Language using Type Inference
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Papers (116)：
Takeshi Ohkawa, Kenta Arai, Kanemitsu Ootsu, Takashi Yokota. Alchemist: A Component-Oriented Development Tool of FPGA based on Publish/Subscribe Model. ICCE. 2024. 1-6
Shun Kojima, Yi Feng, Kazuki Maruta, Kanemitsu Ootsu, Takashi Yokota, Chang Jun Ahn, Vahid Tarokh. Towards Deep Learning-Guided Multiuser SNR and Doppler Shift Detection for Next-Generation Wireless Systems. IEEE Vehicular Technology Conference. 2022. 2022-June
Yoshiki Kimura, Kanemitsu Ootsu, Tatsuya Tsuchiya, Takashi Yokota. Development of RISC-V Based Soft-core Processor with Scalable Vector Extension for Embedded System. ACM International Conference Proceeding Series. 2021. 13-18
Shun Kojima, Yi Feng, Kazuki Maruta, Kanemitsu Ootsu, Takashi Yokota, Chang-Jun Ahn, Vahid Tarokh. Investigation of Input Signal Representation to CNN for Improving SNR Classification Accuracy. VTC Fall. 2021. 1-5
Tomoya Kikuchi, Yoshiki Kimura, Kanemitsu Ootsu, Takashi Yokota. Development of Soft-Core Processor with Efficient Array Data Transfer Mechanism. Proceedings - 2020 8th International Symposium on Computing and Networking Workshops, CANDARW 2020. 2020. 411-415
The Institute of Electronics, Information and Communication Engineers
, The Institute of Systems, Control and Information Engineers
, Information Processing Society of Japan
