Art
J-GLOBAL ID：200902002299477678   Reference number：89A0250635

On the design of fault-tolerant two-dimensional systolic arrays for yield enhancement.

歩留りを向上させたフォルトトレラント2次元シストリックアレイの設計
Author (2)：
KIM J H

About KIM J H

(Univ. Southwestrn Louisiana, LA, USA)

About Univ. Southwestrn Louisiana, LA, USA

, 
REDDY S M

About REDDY S M

(Univ. Iowa, IA, USA)

About Univ. Iowa, IA, USA


Material：
IEEE Transactions on Computers  (IEEE Trans Comput)

About IEEE Transactions on Computers


Volume： 38  Issue： 4  Page： 515-525  Publication year： Apr. 1989 
JST Material Number： C0233A  ISSN： 0018-9340  CODEN： ICTOB4  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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two dimension

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,...
Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
チップ【IC】

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JST classification (2)：
JST classification
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Computer system development 
(JD02010R)

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,  Other digital computer systems 
(JC02050G)

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歩留り

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, 
2次元

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, 
シストリックアレイ

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, 
設計

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