Art
J-GLOBAL ID:200902026880859766   Reference number:86A0317681

Model for delay faults based upon paths.

パスに基づく遅延故障モデル
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Volume: 1985  Page: 342-349  Publication year: 1985 
JST Material Number: E0211B  ISSN: 1089-3539  Document type: Proceedings
Article type: 原著論文  Country of issue: United States (USA)  Language: ENGLISH (EN)
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Logic circuits 
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