Art
J-GLOBAL ID：200902028828646420   Reference number：88A0124821

On delay fault testing in logic circuits.

論理回路における遅延故障検査
Author (2)：
LIN C J

About LIN C J

(Univ. Iowa, IA, USA)

About Univ. Iowa, IA, USA

, 
REDDY S M

About REDDY S M

(Univ. Iowa, IA, USA)

About Univ. Iowa, IA, USA


Material：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (IEEE Trans Comput-Aided Des Integr Circuits Syst)

About IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems


Volume： 6  Issue： 5  Page： 694-703  Publication year： Sep. 1987 
JST Material Number： B0142C  ISSN： 0278-0070  CODEN： ITCSDI  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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logic circuit

About logic circuit

,...
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JST classification (1)：
JST classification
Category name(code) classified by JST.
Logic circuits 
(NC05070B)

About Logic circuits

Terms in the title (3)：
Terms in the title
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論理回路

About 論理回路

, 
遅延故障

About 遅延故障

, 
検査

About 検査


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