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J-GLOBAL ID:200902034258503558   Reference number:88A0046478

Standard cell placement using simulated sintering.

模擬焼結を用いた標準セルの配置
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Volume: 24th  Page: 56-59  Publication year: 1987 
JST Material Number: D0553A  ISSN: 0738-100X  Document type: Proceedings
Article type: 原著論文  Country of issue: United States (USA)  Language: ENGLISH (EN)
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Semiconductor integrated circuit 
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