Art
J-GLOBAL ID：200902060796005321   Reference number：81A0238125

An implicit enumeration algorithm to generate tests for combinational logic circuits.

組合せ論理回路のテスト生成のための列挙アルゴリズム
Author (1)：
GOEL P

About GOEL P

(IBM, NY)

About IBM, NY


Material：
IEEE Transactions on Computers  (IEEE Trans Comput)

About IEEE Transactions on Computers


Volume： 30  Issue： 3  Page： 215-222  Publication year： Mar. 1981 
JST Material Number： C0233A  ISSN： 0018-9340  CODEN： ICTOB4  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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combinational circuit

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,...
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JST classification (2)：
JST classification
Category name(code) classified by JST.
Logic circuits 
(NC05070B)

About Logic circuits

,  Theory of computation 
(JB02000A)

About Theory of computation

Terms in the title (4)：
Terms in the title
Keywords automatically extracted from the title.
組合せ

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, 
論理回路

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, 
テスト生成

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, 
アルゴリズム

About アルゴリズム


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