Art
J-GLOBAL ID：200902067172473112   Reference number：93A0043461

Fault Tolerance of an Information Disseminating Scheme on a Processor Network.

プロセッサネットワークにおける情報伝達体系のフォールトトレランス
Author (3)：
KANAI K

About KANAI K

(Toshiba Corp., Kawasaki-shi, JPN)

About Toshiba Corp., Kawasaki-shi, JPN

, 
IGARASHI Y

About IGARASHI Y

(Gunma Univ., Kiryu-shi, JPN)

About Gunma Univ., Kiryu-shi, JPN

, 
MIURA K

About MIURA K

(Gunma Univ., Kiryu-shi, JPN)

About Gunma Univ., Kiryu-shi, JPN


Material：
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))

About IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)


Volume： E75-A  Issue： 11  Page： 1555-1560  Publication year： Nov. 1992 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)
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fault tolerance

About fault tolerance

,...
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Thesaurus term/Semi thesaurus term
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multiple error

About multiple error


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JST classification (1)：
JST classification
Category name(code) classified by JST.
Computer networks 
(JC03000K)

About Computer networks

Terms in the title (4)：
Terms in the title
Keywords automatically extracted from the title.
プロセッサ

About プロセッサ

, 
情報伝達

About 情報伝達

, 
体系

About 体系

, 
フォールトトレランス

About フォールトトレランス


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