Art
J-GLOBAL ID：200902072473372196   Reference number：90A0183232

Automatic synthesis of asynchronous circuits from high-level specifications.

高水準仕様からの非同期回路の自動合成
Author (3)：
MENG T H-Y

About MENG T H-Y

(Stanford Univ., CA)

About Stanford Univ., CA

, 
BRODERSEN R W

About BRODERSEN R W

(Univ. California, CA)

About Univ. California, CA

, 
MESSERSCHMITT D G

About MESSERSCHMITT D G

(Univ. California, CA)

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Material：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (IEEE Trans Comput-Aided Des Integr Circuits Syst)

About IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems


Volume： 8  Issue： 11  Page： 1185-1205  Publication year： Nov. 1989 
JST Material Number： B0142C  ISSN： 0278-0070  CODEN： ITCSDI  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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asynchronous circuit

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,...
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JST classification (1)：
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Logic circuits 
(NC05070B)

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Terms in the title (3)：
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仕様

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, 
非同期回路

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, 
自動合成

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