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J-GLOBAL ID:200902075285896519   Reference number:91A0007912

Sequential circuit verification using symbolic model checking.

記号モデルチェックを使った順序回路の検証
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Volume: 27th  Page: 46-51  Publication year: 1990 
JST Material Number: D0553A  ISSN: 0738-100X  Document type: Proceedings
Article type: 原著論文  Country of issue: United States (USA)  Language: ENGLISH (EN)
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Logic circuits 
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