Art
J-GLOBAL ID：200902079084813874   Reference number：86A0415152

Reconfigurable architectures for VLSI processing arrays.

VLSI処理アレイのための再構成可能なアーキテクチャ
Author (2)：
SAMI M

About SAMI M

(Politecnico di Milano, Italy)

About Politecnico di Milano, Italy

, 
STEFANELLI R

About STEFANELLI R

(Politecnico di Milano, Italy)

About Politecnico di Milano, Italy


Material：
Proceedings of the IEEE  (Proc IEEE)

About Proceedings of the IEEE


Volume： 74  Issue： 5  Page： 712-722  Publication year： May. 1986 
JST Material Number： D0378A  ISSN： 0018-9219  CODEN： IEEPAD  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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VLSI

About VLSI

,...
Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
フォルトトレラント

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JST classification (1)：
JST classification
Category name(code) classified by JST.
Special-purpose arithmetic and control units 
(JC04030Y)

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Terms in the title (4)：
Terms in the title
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VLSI

About VLSI

, 
アレイ

About アレイ

, 
再構成

About 再構成

, 
アーキテクチャ

About アーキテクチャ


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