Art

J-GLOBAL ID：200902103855553177   Reference number：97A0289146

Analog Circuit Techniques for System-on-Chip Integration. Approaches to Reducing Digital-Noise Coupling in CMOS Mixed-Signal LSIs.

CMOS混在信号LSIにおけるディジタル雑音結合を減少する手法

Author (2)： TSUKADA T (Hitachi, Ltd., Kokubunji-shi, JPN) ,  MAKIE-FUKUDA K (Hitachi, Ltd., Kokubunji-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E80-A  Issue： 2  Page： 263-275  Publication year： Feb. 1997 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： noise reduction ,...
Semi thesaurus term： アナログ・ディジタル混載LSI

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JST classification (2)： General  (NC03161C) ,  Noise in general  (ND04010J)

Reference (44)：

• HODGES, D. A. Potential of MOS technologies for analog integrated circuits. IEEE J. Solid-State Circuits. 1978, SC-13, 3, 285-294
• SAUL, P. Practical limits of A/D and D/A conversion. IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers. 1989, 104-105
• DUMLUGOL, D. The analog and mixed-signal bottleneck in the 90s. How to resolve it?. Proc. IEEE Custom Integrated Circuits Conf. 1993
• HUBER, W. Impediments to mixed-signal IC development. IEEE Int. Solid-State Circuits Conf. Dig. Tech. 1991, 200-201
• TSUKADA, T. Study on offset error characteristics in CMOS autozeroed choppertype comparators. IEICE Trans. 1994, J77-C-II, 11, 516-524

Terms in the title (5)： CMOS ,  LSI ,  ディジタル ,  雑音 ,  手法