Art
J-GLOBAL ID：200902108614185039
Reference number：02A0816565
Test and Verification of VLSI. Symbolic Model Checking of Deadlock Free Property of Task Control Architecture.
VLSIのテストと検証 タスク制御アーキテクチャのデッドロック無し特性の記号モデル検査法
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Author (1)：
Material：
Volume：
E85-D
Issue：
10
Page：
1579-1586
Publication year：
Oct. 01, 2002
JST Material Number：
L1371A
ISSN：
0916-8532
Document type：
Article
Article type：
原著論文
Country of issue：
Japan (JPN)
Language：
ENGLISH (EN)
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JST classification (2)：
JST classification
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Computer system development
, General
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