Art
J-GLOBAL ID：200902116270415571
Reference number：98A0874588
A Sub-1V Triple-Threshold CMOS/SIMOX Circuit for Active Power Reduction.
能動電力低減用の1V未満の三重しきい値CMOS/SIMOX回路
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Author (3)：
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Material：
Volume：
41
Page：
190-191,436
Publication year：
Feb. 1998
JST Material Number：
D0753A
ISSN：
0193-6530
Document type：
Proceedings
Article type：
短報
Country of issue：
United States (USA)
Language：
ENGLISH (EN)
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JST classification (2)：
JST classification
Category name(code) classified by JST.
Semiconductor integrated circuit
, Logic circuits
Terms in the title (5)：
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