Art
J-GLOBAL ID：200902126793734960
Reference number：96A0930002
Synthesis and Verification of Hardware Design. A Floorplan Based Methodology for Data-Path Synthesis of Sub-Micron ASICs.
サブミクロンASICのデータパス合成にたいするフロアプランに基づく方法
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Author (2)：
,
Material：
Volume：
E79-D
Issue：
10
Page：
1389-1395
Publication year：
Oct. 1996
JST Material Number：
L1371A
ISSN：
0916-8532
Document type：
Article
Article type：
原著論文
Country of issue：
Japan (JPN)
Language：
ENGLISH (EN)
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