Art

J-GLOBAL ID：200902148373953295   Reference number：97A0632186

A Low Power 622 MHz CMOS Phase-Locked Loop with Source Coupled VCO and Dynamic PFD.

ソース結合VCOと動的PFDを持った低電力622MHz CMOS位相同期ループ

Author (4)： YOSHIZAWA H (Kyushu UNiv., Fukuoka-shi, JPN) ,  TANIGUCHI K (Kyushu UNiv., Fukuoka-shi, JPN) ,  SHIRAHAMA H (Kyushu UNiv., Fukuoka-shi, JPN) ,  NAKASHI K (Kyushu UNiv., Fukuoka-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E80-A  Issue： 6  Page： 1015-1020  Publication year： Jun. 1997 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： phase locked loop ,...
Semi thesaurus term： energy saving

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JST classification (1)： Other electronic circuits  (NC05090X)

Reference (8)：

• NOTANI, H. A 622MHz CMOS phase-locked loop with precharge-type phase frequency detector. 1994 Symposium of VLSI circuits, Digest of Technical Papers. 1994, 129-130
• SHIRAHAMA, H. A new very fast pull-in PLL system with anti pseudo lock function. 1993 Symposium of VLSI circuits, Digest of Technical Papers. 1993, 75-76
• ALVAREZ, J. A wide-bandwidth low-voltage PLL for powerPCTM microprocessors. 1994 Symposium of VLSI circuits, Digest of Technical Papers. 1994, 37-38
• YOSHIZAWA, H. A low power phase frequency detector with dynamic structure. Proc. of the 1996 IEICE general conference. 1996, 284
• RAZABI, B. Design of Monolithic Phase-Locked Loops and Clock Recovery Circuits. 1996, 24-29

Terms in the title (6)： ソース ,  VCO ,  PFD ,  低電力 ,  CMOS ,  位相同期ループ