Art
J-GLOBAL ID:200902152661535560   Reference number:96A0412810

A high-speed clock distributing system using guarded transmission lines.

ガード付き伝送線路を用いた高速クロック分配システム
Author (2):
Material:
Volume: 1995  Page: 323-326  Publication year: 1995 
JST Material Number: W0080A  Document type: Proceedings
Article type: 原著論文  Country of issue: United States (USA)  Language: ENGLISH (EN)
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JST classification (2):
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Logic circuits  ,  Oscillation circuits 
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