Art
J-GLOBAL ID：200902174960129806
Reference number：98A0843860
VLSI Considerations for TESH: A New Hierarchical Interconnection Network for 3-D Integration.
TESH用VLSIの考察 3D集積化用の新しい階層的相互接続回路網
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Author (2)：
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Material：
Volume：
6
Issue：
3
Page：
346-353
Publication year：
Sep. 1998
JST Material Number：
W0516A
ISSN：
1063-8210
CODEN：
ITCOB4
Document type：
Article
Article type：
原著論文
Country of issue：
United States (USA)
Language：
ENGLISH (EN)
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JST classification (1)：
JST classification
Category name(code) classified by JST.
Semiconductor integrated circuit
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