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J-GLOBAL ID：200902175320892453   Reference number：93A0632464

Modeling and Analysis of Vias in Multilayered Integrated Circuits.

多層集積回路のバイアのモデル化と解析
Author (3)：
GU Q

About GU Q

(Massachusetts Inst. Technology, MA)

About Massachusetts Inst. Technology, MA

, 
YANG Y E

About YANG Y E

(Massachusetts Inst. Technology, MA)

About Massachusetts Inst. Technology, MA

, 
TASSOUDJI M A

About TASSOUDJI M A

(Massachusetts Inst. Technology, MA)

About Massachusetts Inst. Technology, MA


Material：
IEEE Transactions on Microwave Theory and Techniques  (IEEE Trans Microw Theory Tech)

About IEEE Transactions on Microwave Theory and Techniques


Volume： 41  Issue： 2  Page： 206-214  Publication year： Feb. 1993 
JST Material Number： C0229A  ISSN： 0018-9480  CODEN： IETMAB  Document type： Article
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
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multistory structure

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,...
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JST classification (1)：
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Semiconductor integrated circuit 
(NC03162T)

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Terms in the title (4)：
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多層

About 多層

, 
集積回路

About 集積回路

, 
モデル化

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, 
解析

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