Art

J-GLOBAL ID：200902181764626687   Reference number：00A0559648

Dynamically Variable Line-Size Cache Architecture for Merged DRAM/Logic LSIs.

DRAM/Logic合成型LSIのための動的ライン長可変型キャッシュアーキテクチャ

Author (3)： INOUE K (Kyushu Univ., Kasuga-shi, JPN) ,  KAI K (Inst. System & Information Technol./KYUSHU, Fukuoka-shi, JPN) ,  MURAKAMI K (Kyushu Univ., Kasuga-shi, JPN)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E83-D  Issue： 5  Page： 1048-1057  Publication year： May. 25, 2000 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *cache memory ,...

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JST classification (1)： Memory systems  (JC02040V)

Reference (18)：

• DAHLGREN, F. Fixed and adaptive sequential prefetching in shared memory multi processors. Proc.1993 International Conference on Paral lel Processing. 1993, 56-63
• DUBNICKI, C. Adjustable block size coherent caches. Proc. 19th Annual International Symposium on Computer Architecture. 1992, 170-180
• GONZALEZ, A. A data cache with multiple caching strategies tuned to different types of locality. Proc. International Conference on Supercomputing. 1995, 338-347
• HILL, M. D. A case for direct-mapped caches. IEEE Conputer. 1988, 21, 12, 25-40
• HILL, M. D. WARTS: Wisconsin Architectural Research Tool Set. http://www.cs.wisc.edu/~larus/warts.html

Terms in the title (5)： DRAM ,  LSI ,  変型 ,  キャッシュ ,  アーキテクチャ