Reduction of Charge Build-Up during Reactive Ion Etching by Using Silicon-On-Insulator Structures.

ARITA K; AKAMATSU M; ASANO T

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J-GLOBAL ID：200902186005020040 Reference number：97A0501308

Reduction of Charge Build-Up during Reactive Ion Etching by Using Silicon-On-Insulator Structures.

絶縁体上シリコン構造を用いることによる反応性イオンエッチング中の電荷蓄積の減少

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Material：
Volume： 36 Issue： 3B Page： 1505-1508 Publication year： Mar. 1997
JST Material Number： G0520B ISSN： 0021-4922 Document type： Article
Article type：原著論文 Country of issue： Japan (JPN) Language： ENGLISH (EN)

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Applications of plasma , Metal-insulator-semiconductor structures , Manufacturing technology of solid-state devices

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ARITA, K. Tech.Dig.1996 Microprocess Conf. 1996, 158
LAI, K. IEEE Electron Device Lett. 1996, 17, 82
MCVITTIE, J. P. Proc.1st Int.Symp.Plasma Process-Induced Damage. 1996, 7

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