Art
J-GLOBAL ID：200902187742325754   Reference number：97A0015416

Interconnect Scaling-The Real Limiter to High Performance ULSI.

配線スケーリング 高性能ULSIの現実的制限
Author (1)：
BOHR M T

About BOHR M T

(Intel Corp., OR, USA)

About Intel Corp., OR, USA


Material：
Technical Digest. International Electron Devices Meeting  (IEEE International Electron Devices Meeting)

About Technical Digest. International Electron Devices Meeting


Volume： 1995  Page： 241-244  Publication year： 1995 
JST Material Number： C0829B  ISSN： 0163-1918  Document type： Proceedings
Article type： 原著論文  Country of issue： United States (USA)  Language： ENGLISH (EN)
Thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
VLSI

About VLSI

,...
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JST classification (1)：
JST classification
Category name(code) classified by JST.
General 
(NC03161C)

About General

Terms in the title (4)：
Terms in the title
Keywords automatically extracted from the title.
スケーリング

About スケーリング

, 
高性能

About 高性能

, 
ULSI

About ULSI

, 
制限

About 制限


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