Art

J-GLOBAL ID：200902204435030692   Reference number：05A1024520

Logic Synthesis Technique for High Speed Differential Dynamic Logic with Asymmetric Slope Transition

非対称傾斜遷移をもつ高速差動動的論理のための論理合成技法

Author (4)： MORIMOTO Masao (Kobe Univ., Kobe-shi, JPN) ,  TANAKA Yoshinori (Kobe Univ., Kobe-shi, JPN) ,  NAGATA Makoto (Kobe Univ., Kobe-shi, JPN) ,  TAKI Kazuo (Kobe Univ., Kobe-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E88-A  Issue： 12  Page： 3324-3331  Publication year： Dec. 01, 2005 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *logical design ,...
Semi thesaurus term： BDD(graph) ,...

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JST classification (2)： General  (NC03161C) ,  CAD,CAM  (JE10000A)

Reference (14)：

• NG, P. Performance of CMOS differential circuits. IEEE J. Solid-State Circuits. 1996, 31, 6, 841-846
• KRAMBECK, R. H. High-speed compact circuits with CMOS. IEEE J. Solid-State Circuits. 1982, SC-17, 3, 614-619
• CHU, K. M. A comparison of CMOS circuit techniques : Differential cascode voltage switch logic versus conventional logic. IEEE J. Solid-State Circuits. 1987, 22, 4, 528-532
• HELLER, L. G. Cascode voltage switch logic : A differential CMOS logic family. IEEE International Solid-State Circuits Conference, Feb. 1984. 1984, 16-17
• CHU, K. M. Design procedures for differential cascode voltage switch circuits. IEEE J. Solid-State Circuits. 1986, 21, 6, 1082-1087

Terms in the title (6)： 非対称 ,  遷移 ,  差動 ,  動的論理 ,  論理合成 ,  技法