Art
J-GLOBAL ID：200902208742758259   Reference number：03A0325895

FPGA Speed Improvement mixing Multiple Gate Width Routing Switches

複数ゲート幅の配線スイッチの混在によるFPGAの動作速度向上
Author (2)：
MATSUMOTO YOHEI

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(岡山大 大学院自然科学研究科)

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, 
MASAKI AKIRA

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(岡山大 工)

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Material：
電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))

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Volume： 102  Issue： 685(ICD2002 211-219)  Page： 43-48  Publication year： Mar. 06, 2003 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)
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*FPGA

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,...
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Elmore遅延

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JST classification (1)：
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Category name(code) classified by JST.
Semiconductor integrated circuit 
(NC03162T)

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Terms in the title (3)：
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ゲート幅

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, 
FPGA

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, 
動作速度

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