Art

J-GLOBAL ID：200902209769745864   Reference number：03A0852710

Irredundant Low Power Address Bus Encoding Techniques Based on Adaptive Codebooks

適応コードブックに基づく非冗長低電力アドレスバス符号化手法

Author (2)： KOMATSU S (Univ. Tokyo, Tokyo, JPN) ,  FUJITA M (Univ. Tokyo, Tokyo, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E86-A  Issue： 12  Page： 3001-3008  Publication year： Dec. 01, 2003 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *data bus ,...
Semi thesaurus term： system bus ,...

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JST classification (2)： I/O interfaces  (JC04040J) ,  CAD,CAM  (JE10000A)

Reference (12)：

• STAN, M.R. Bus-invert coding for low power I/O. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 1995, 3, 1, 49-58
• BENINI, L. Asymptotic zero-transition activity encoding for address busses in low-power microprocessor-based systems. IEEE 7th Great Lakes Symposium on VLSI, March, 1997. 1997, 77-82
• BENINI, L. Address bus encoding techniques for system-level power optimization. Design Automation and Test in Europe, 1998. 1998, 861-866
• KOMATSU, S. Bus data encoding with coupling-driven adaptive code-book method for low power data transmission. 27th European Solid-State Circuits Conference, Sept., 2001. 2001, 312-315
• AGHAGHIRI, Y. Irredundant address bus encoding for low power. International Symposium on Low Power Electronics and Design'01. 2001, 182-187

Terms in the title (7)： 適応 ,  コードブック ,  冗長 ,  低電力 ,  アドレスバス ,  符号化 ,  手法