Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

PANDE Partha Pratim; GRECU Cristian; JONES Michael; IVANOV Andre; SALEH Resve

Art

J-GLOBAL ID：200902215832389844 Reference number：05A0668221

Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures

ネットワーク-オン-チップ相互接続アーキテクチャに関するパフォーマンス評価と設計トレードオフ

Publisher site Copy service {{ this.onShowCLink("http://jdream3.com/copy/?sid=JGLOBAL&noSystem=1&documentNoArray=05A0668221&COPY=1") }}
Access JDreamⅢ for advanced search and analysis. {{ this.onShowJLink("http://jdream3.com/lp/jglobal/index.html?docNo=05A0668221&from=J-GLOBAL&jstjournalNo=C0233A") }}

Author (5)： , , , ,
Material：
Volume： 54 Issue： 8 Page： 1025-1040 Publication year： Aug. 2005
JST Material Number： C0233A ISSN： 0018-9340 CODEN： ICTOB4 Document type： Article
Article type：原著論文 Country of issue： United States (USA) Language： ENGLISH (EN)

,...
,...

To see more with JDream III (charged). {{ this.onShowAbsJLink("http://jdream3.com/lp/jglobal/index.html?docNo=05A0668221&from=J-GLOBAL&jstjournalNo=C0233A") }}

Computer networks , I/O interfaces

, , , ,

Return to Previous Page