Characteristics Improvement of PLLs Using Phase Interpolation
位相補間によるPLLの特性改善
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Volume:
42
Issue:
10
Page:
1175-1180
Publication year:
Oct. 31, 2006
JST Material Number:
S0104A
ISSN:
0453-4654
CODEN:
KJSRA
Document type:
Article
Article type:
原著論文
Country of issue:
Japan (JPN)
Language:
JAPANESE (JA)
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JST classification (1):
JST classification
Category name(code) classified by JST.
HEYDARI, P. Characterizing the effects of the PLL jitter due to substrate noise in discrete-time delta-sigma modulators. IEEE Trans. Circuits and Systems I, Fundam. Theory Appl. 2005, 52, 6, 1073-1085
LIU, Rui-feng. A Fully Symmetrical PFD for Fast Locking Low Jitter PLL. Int. Conf. on ASIC. Proc., 2003. 2003, 2, 725-727