Art

J-GLOBAL ID：200902247350363669   Reference number：06A0423956

A Highly Linearized CMOS Multiplier with a Controlled Tail Current Source

テイルが制御された電流源を備えた高度線型化CMOS乗算器

Author (3)： SHOUNO Kazuhiro (Univ. Tsukuba, Tsukuba-shi, JPN) ,  HORI Tasuku (Univ. Tsukuba, Tsukuba-shi, JPN) ,  ISHIBASHI Yukio (Univ. Tsukuba, Tsukuba-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E89-A  Issue： 6  Page： 1533-1539  Publication year： Jun. 01, 2006 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *multiplier ,...
Semi thesaurus term： MOS transistor ,...

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JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Electronic circuits in general  (NC05010N)

Reference (17)：

• WANG, Z. A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance. IEEE J. Solid-State Circuits. 1991, 26, 9, 1293-1301
• BABANEZHAD, J. N. A 20-V four-quadrant CMOS analog multiplier. IEEE J. Solid-State Circuits. 1985, SC-20, 6, 1158-1168
• SZCZEPANSKI, S. Highly linear voltage-controlled CMOS transconductors. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. 1993, 40, 4, 258-262
• QIN, S. A ±5-V CMOS analog multiplier. IEEE J. Solid-State Circuits. 1987, SC-22, 6, 1143-1146
• BULT, K. A CMOS four-quadrant analog multiplier. IEEE J. Solid-State Circuits. 1986, SC-21, 3, 430-435

Terms in the title (6)： テイル ,  電流源 ,  高度 ,  線型 ,  CMOS ,  乗算器