Art

J-GLOBAL ID：200902249814536149   Reference number：07A0140702

A Systolic FPGA Architecture of Two-Level Dynamic Programming for Connected Speech Recognition

連続音声認識のための2水準動的計画法のシストリックFPGAアーキテクチャ

Author (2)： KIM Yong (POSTECH, Kyungbuk, KOR) ,  JEONG Hong (POSTECH, Kyungbuk, KOR)
Material： IEICE Transactions on Information and Systems (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Inf Syst (Inst Electron Inf Commun Eng))
Volume： E90-D  Issue： 2  Page： 562-568  Publication year： Feb. 01, 2007 
JST Material Number： L1371A  ISSN： 0916-8532  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *continuous speech recognition ,...
Semi thesaurus term： propagation delay

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JST classification (2)： Pattern recognition  (JE07000S) ,  Special-purpose arithmetic and control units  (JC04030Y)

Reference (15)：

• UPADHYAYA, V. A parallel VLSI implementation of Viterbi algorithm for accelerated word recognition. VLSI, 1993. Design Automation of High Performance VLSI Systems, Proceedings. Third Great Lakes Symposium on. 1993, 37-41
• KIM, B.-S. Low power Viterbi search architecture using inverse hidden Markov model. Signal Processing Systems, 2000. SiPS 2000. 2000 IEEE Workshop on. 2000, 724-732
• VARGAS, F. L. A FPGA-based Viterbi algorithm implementation for speech recognition systems. Acoustics, Speech, and Signal Processing, 2001. Proceedings. (ICASSP '01), 2001 IEEE International Conference on. 2001, 2, 1217-1220
• JOU, J. M. An efficient VLSI architecture for HMM-based speech recognition. Electronics, Circuit and Systems, 2001. ICECS 2001. The 8th IEEE International Conference. 2001, 1, 469-472
• PARK, B.-G. Low power VLSI architecture of Viterbi scorer for HMM-based isolated word recognition. Quality Electronic Design, 2002. Proceedings. International Symposium on. 2002, 235-239

Terms in the title (5)： 連続音声認識 ,  水準 ,  動的計画法 ,  FPGA ,  アーキテクチャ