Art

J-GLOBAL ID：200902262317661424   Reference number：05A0522403

Super-high Speed, Accuracy, and Modularized Residue Number System based on Redundant Binary Representation

冗長二進法に基づく超高速・高精度・モジュール化剰余系

Author (5)： NAKAMURA Tsugio (Kokusai Junior Coll., Tokyo) ,  ABE Kazuhiro (Fujitsu LTD., Tokyo) ,  FUYUTSUME Narito (Tokyo Denki Univ., Chiba) ,  KASAHARA Hiroshi (Tokyo Denki Univ., Chiba) ,  TANAKA Teruo (Tokyo Denki Univ., Tokyo)
Material： 電気学会論文誌 C  (IEEJ Transactions on Electronics, Information and Systems)
Volume： 125  Issue： 6  Page： 879-886  Publication year： Jun. 01, 2005 
JST Material Number： S0810A  ISSN： 0385-4221  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： redundant method ,...
Semi thesaurus term： binary system ,...

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JST classification (1)： Numerical computation  (JE02000J)

Reference (17)：

• AVIZEINIS, A. Signed Digit Number Representations for Fast Parallel Arithmetic. IRE Trans. Electronic Comput. 1961, KC-10, 9, 389-400
• BIRNBAUM, H. M. How VSIA Answers the SOC Dilemma. IEEE Computer. 1999, Jun, 42-50
• NAKANO, E. Fast Asynchronous Nonrestoring Division with Signed Digit Representation. Technical Report of IEICE of Japan, April. 1999, ICD99-9, 21-28
• TAKAGI, N. A VLSI-Oriented High-Speed Divider Using Redundant Binary Representation. Trans. IEICE of Japan, D. 1984, J67, 4, 450-457
• ISHII, S. 2040-bit High-Speed Modulus Processor for Public Key Encryption. Trans. IEICE of Japan, D-I. 1999, J82, 4, 571-580

Terms in the title (3)： 冗長 ,  モジュール化 ,  剰余系