Art

J-GLOBAL ID：200902274478660949   Reference number：03A0852715

DFT Timing Design Methodology for Logic BIST

論理BISTのためのDFTタイミング設計の方法論

Author (5)： SATO Y (Hitachi, Ltd., Ome-shi, JPN) ,  SATO M (Hitachi, Ltd., Ome-shi, JPN) ,  TSUTSUMIDA K (Hitachi, Ltd., Ome-shi, JPN) ,  HATAYAMA K (Hitachi, Ltd., Kodaira-shi, JPN) ,  NOMOTO K (Hitachi, Ltd., Kodaira-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E86-A  Issue： 12  Page： 3049-3055  Publication year： Dec. 01, 2003 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： LSI ,...

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JST classification (2)： Measurement,testing and reliability of solid-state devices  (NC03040G) ,  CAD,CAM  (JE10000A)

Reference (19)：

• STAPPER, C. H. Modeling of defects in integrated circuit photolithographic patterns. IBM J. Research & Development. 1984, 28, 4, 461-475
• International technology roadmap for semiconductors
• FOOTE, T. G. Testing the 400 MHz IBM generation-4 CMOS chip. Proc. IEEE International Test Conference, 1997. 1997, 106-114
• GILLIS, P. S. Test methodologies and design automation for IBM ASICs. IBM J. Research & Development. 1996, 40, 4, 461-474
• BRADEN, J. Use of BIST in SUN FIRE^TM servers. Proc. IEEE International Test Conference, 2001. 2001, 1017-1022

Terms in the title (5)： 論理 ,  BIST ,  DFT ,  設計 ,  方法論