Art

J-GLOBAL ID：200902274575445807   Reference number：09A0650080

Evaluation of a High-speed Classification System using Dynamic and Partial Reconfiguration

高速パターン認識システムのための動的な再構成手法の評価と比較

Author (3)： KAWAI HIROYUKI (筑波大) ,  YAMAGUCHI YOSHIKI (筑波大) ,  YASUNAGA MORITOSHI (筑波大)
Material： 電子情報通信学会技術研究報告  (IEICE Technical Report (Institute of Electronics, Information and Communication Engineers))
Volume： 109  Issue： 26(RECONF2009 1-18)  Page： 73-78  Publication year： May. 07, 2009 
JST Material Number： S0532B  ISSN： 0913-5685  Document type： Proceedings
Article type： 原著論文  Country of issue： Japan (JPN)  Language： JAPANESE (JA)

Thesaurus term： *pattern recognition ,  *reconstitution ,  *FPGA ,  micro circuit technique ,  prototype ,  dynamic reconfiguration ,  action and behavior
Semi thesaurus term： on chip

JST classification (2)： Pattern recognition  (JE07000S) ,  Semiconductor integrated circuit  (NC03162T)

Reference (11)：

• 樋口哲也. 進化型ハードウェア. 情報処理. 1999, 40, 8, 795-800
• YASUNAGA, M. Evolvable Sonar Spectrum Discrimination Chip Designed by Genetic Algorithm. Systems, Man and Cybernetics. 5, 585590
• YASUNAGA, M. The Kernel-based Pattern Recognition System Designed by Genetic Algorithms. IEICE Transaction on Information and Systems, D. 2001, E84-D, 11, 1528-1539
• KAWAI, H. An Adaptive Pattern Recognition Hardware with On-chip Shft Register-based Partial Reconfuguration. Proc. International Conference on Filed-Programmable Technology (ICFPT'08), December. 2008, 169-176
• SEKANINA, L. Design of the Special fast reconfigurable chip using common FPGAs. Proc. of Design and Diagnostics of Electronic Circuits and Systems, 2000. 2000, 161-168

Terms in the title (4)： パターン認識 ,  再構成 ,  手法 ,  評価