Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm

MASUI Shoichi; MUKAIDA Kenji; TAKENAKA Masahiko; TORII Naoya

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J-GLOBAL ID：200902276218051607 Reference number：05A0318105

Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm

RSAアルゴリズムに使用する高速度で面積効率の良い低電力Montgomeryモジュール型乗算器の設計最適化

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Material：
Volume： E88-C Issue： 4 Page： 576-581 Publication year： Apr. 01, 2005
JST Material Number： L1370A ISSN： 0916-8524 Document type： Article
Article type：原著論文 Country of issue： Japan (JPN) Language： ENGLISH (EN)

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Arithmetic systems , Code theory

Reference (10)：

RIVEST, R. A method of obtaining digital signature and public key cryptosystems. Commun. ACM. 1978, 21, 2, 120-126
MASUI, S. FeRAM applications for next-generation smart card LSIs. Extended Abstracts of 1st International Meeting on Ferroelectric Random Access Memories, 2001. 2001, 13-14
MUKAIDA, K. Design of high-speed and area-efficient Montgomery modular multiplier for RSA algorithm. Symp. on VLSI Circuits Digests of Technical Papers, 2004. 2004, 320-323
MONTGOMERY, P. Modular multiplication without trial division. Mathematics of Computation. 1985, 44, 170, 519-521
KOC, C. K. High-speed RSA implementation. 1994

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