Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor

KUMAKI Takeshi; ISHIZAKI Masakatsu; KOIDE Tetsushi; MATTAUSCH Hans Juergen; KURODA Yasuto; NODA Hideyuki; DOSAKA Katsumi; ARIMOTO Kazutami; SAITO Kazunori

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J-GLOBAL ID：200902278799957361 Reference number：07A0791514

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix Processor

超並列メモリー埋込SIMDマトリクスプロセッサを用いた離散コサイン変換処理の高速化

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Material：
Volume： E90-D Issue： 8 Page： 1312-1315 Publication year： Aug. 01, 2007
JST Material Number： L1371A ISSN： 0916-8532 Document type： Article
Article type：原著論文 Country of issue： Japan (JPN) Language： ENGLISH (EN)

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Special-purpose arithmetic and control units

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NAKAJIMA, M. A 40GOPS 250mW massively parallel processor based on matrix architecture. ISSCC Dig. Tech. Papers, Feb. 2006. 2006, 410-412
TANIZAKI, T. A super parallel SIMD processor with time/space conversion bus bridge on the matrix architecture. IEICE Technical Report. 2006, ICD2006-79
SAKAI, Y. The image information coding. 2001, 118-120

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