Art

J-GLOBAL ID：200902293279154834   Reference number：08A0546207

Design of Low Power Track and Hold Circuit Based on Two Stage Structure

二段構造に基づいた低電力トラックアンドホールド回路の設計

Author (4)： SATO Takahide (Tokyo Inst. of Technol., Tokyo, JPN) ,  MATSUMOTO Isamu (ROHM CO., LTD, Yokohama-shi, JPN) ,  TAKAGI Shigetaka (Tokyo Inst. of Technol., Tokyo, JPN) ,  FUJII Nobuo (Tokyo Inst. of Technol., Tokyo, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E91-C  Issue： 6  Page： 894-902  Publication year： Jun. 01, 2008 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *signal converter ,  *sample holding circuit ,  *circuit design ,  consumed electric power ,  modification ,  analog to digital converter ,  cascade connection ,  AD conversion
Semi thesaurus term： トラックアンドホールド回路

JST classification (1)： AD/DA conversion circuits  (NC05080M)

Reference (9)：

• LIU, F. CMOS folding and interpolating A/D converter with differential compensative T/H circuit. Proc. 2003 IEEE Conference on Electron Devices and Solid-StateCircuits. 2003, 453-456
• SATO, T. 4GB/s track and hold circuit using parasitic capacitance canceler. Proc. European Solid-State Circuits Conference, 2004. 2004, 347-350
• KARANICOLAS, A. N. A 2.7-V 300-MS/s track-and-hold amplifier. IEEE J. Solid-State Circuits. 1997, 32, 1961-1967
• JOHNS, D. A. Analog integrated circuit design. 1997
• VAN DE PLASSCHE, Ruby. CMOS integrated analog to digital and digital to analog converters. 2003

Terms in the title (3)： 二段構造 ,  低電力 ,  設計