Art
J-GLOBAL ID：200902294338386732   Reference number：06A0805345

Secure Scan: A Design-for-Test Architecture for Crypto Chips

安全スキャン 暗号チップのためのテスト用設計アーキテクチャ
Author (3)：
YANG Bo

About YANG Bo

(Polytechnic Univ., NY, USA)

About Polytechnic Univ., NY, USA

, 
WU Kaijie

About WU Kaijie

(Univ. Illinois, IL, USA)

About Univ. Illinois, IL, USA

, 
KARRI Ramesh

About KARRI Ramesh

(Polytechnic Univ., NY, USA)

About Polytechnic Univ., NY, USA


Material：
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (IEEE Trans Comput-Aided Des Integr Circuits Syst)

About IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems


Volume： 25  Issue： 10  Page： 2287-2293  Publication year： Oct. 2006 
JST Material Number： B0142C  ISSN： 0278-0070  CODEN： ITCSDI  Document type： Article
Article type： 短報  Country of issue： United States (USA)  Language： ENGLISH (EN)
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*cryptogram

About cryptogram

,...
Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
testability

About testability


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JST classification (1)：
JST classification
Category name(code) classified by JST.
Code theory 
(ND02030R)

About Code theory

Terms in the title (5)：
Terms in the title
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スキャン

About スキャン

, 
暗号

About 暗号

, 
テスト

About テスト

, 
設計

About 設計

, 
アーキテクチャ

About アーキテクチャ


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