Art

J-GLOBAL ID：200902299218892490   Reference number：07A0337832

Asymmetric Slope Dual Mode Differential Logic Circuit for Compatibility of Low-Power and High-Speed Operations

低電力と高速動作を両立させる非対称傾斜デュアルモード微分論理回路

Author (3)： MORIMOTO Masao (Kobe Univ., Kobe-shi, JPN) ,  NAGATA Makoto (Kobe Univ., Kobe-shi, JPN) ,  TAKI Kazuo (Kobe Univ., Kobe-shi, JPN)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E90-C  Issue： 4  Page： 675-682  Publication year： Apr. 01, 2007 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *high speed ,...

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JST classification (2)： Logic circuits  (NC05070B) ,  Semiconductor integrated circuit  (NC03162T)

Reference (10)：

• USAMI, K. Automated selective multi-threshold design for ultra-low standby applications. ISLPED02. 2002, 202-206
• MUTOH, S. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS. IEEE J. Solid-State Circuits. 1995, 30, 8, 847-854
• NG, P. Performance of CMOS differential circuits. IEEE J. Solid-State Circuits. 1996, 31, 6, 841-846
• HELLER, L. G. Cascode-voltage switch logic : A differential CMOS logic family. IEEE International Solid-State Circuits Conference, Feb. 1984. 1984, 16-17
• CHU, K. M. A comparison of CMOS circuit techniques : Differential cascode voltage switch logic versus conventional logic. IEEE J. Solid-State Circuits. 1987, 22, 4, 528-532

Terms in the title (6)： 低電力 ,  高速動作 ,  非対称 ,  デュアルモード ,  微分 ,  論理回路