Art

J-GLOBAL ID：201002215560006488   Reference number：10A1755348

Reduction of Area per Good Die for SoC Memory Built-In Self-Test

SoCメモリ組み込み自己テストのための良好チップあたりの領域低減

Author (5)： ARAI Masayuki (Tokyo Metropolitan Univ., Hino-shi, JPN) ,  ENDO Tatsuro (Tokyo Metropolitan Univ., Hino-shi, JPN) ,  IWASAKI Kazuhiko (Tokyo Metropolitan Univ., Hino-shi, JPN) ,  NAKAO Michinobu (Renesas Technol. Corp., Kodaira-shi, JPN) ,  SUZUKI Iwao (Renesas Technol. Corp., Kodaira-shi, JPN)
Material： IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Fundam Electron Commun Comput Sci (Inst Electron Inf Commun Eng))
Volume： E93-A  Issue： 12  Page： 2463-2471  Publication year： Dec. 01, 2010 
JST Material Number： F0699C  ISSN： 0916-8508  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： VLSI ,  *SRAM ,  built-in self-test ,  *semiconductor chip ,  coder ,  comparator ,  repair ,  fault detection ,  algorithm ,  benchmark ,  statistical analysis
Semi thesaurus term： *SOC ,  repair ,  redundancy analysis ,  diagnosis algorithm ,  *BIST ,  comparator ,  encoder

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Numerical computation  (JE02000J)

Reference (13)：

• International Technology Roadmap for Semiconductors. 2009
• ADAMS, R. D. High Performance Memory Testing. 2003
• DU, X. Full-speed field-programmable memory BIST architecture. International Test Conference, 2005. 2005, 1165-1173
• SHOUKOURIAN, S. SoC yield optimization via an embedded-memory test and repair infrastructure. IEEE Des. Test Comput. 2004, 21, 3, 200-207
• HUANG, R.-F. Economic aspects of memory built-in self-repair. IEEE Des. Test Comput. 2007, 24, 2, 164-172

Terms in the title (2)： SOC ,  組み込み自己テスト