Art
J-GLOBAL ID：201002224774342352
Reference number：10A0440790
Improvement of Data Transfer Efficiency between PEs in a Massively Parallel Processor
超並列プロセッサコアにおけるPE間データ転送効率の改善
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Author (5)：
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Material：
Volume：
2009
Issue：
2
Page：
SURIMODERU.VOL.2,NO.3,64-74
Publication year：
Apr. 15, 2010
JST Material Number：
L7379A
ISSN：
1882-7772
Document type：
Article
Article type：
原著論文
Country of issue：
Japan (JPN)
Language：
JAPANESE (JA)
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Semi thesaurus term：
Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
On J-GLOBAL, this item will be available after more than half a year after the record posted. In addtion, medical articles require to login to MyJ-GLOBAL.
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JST classification (3)：
JST classification
Category name(code) classified by JST.
Digital computer systems in general
, Special-purpose arithmetic and control units
, Network methods
Reference (12)：
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富田眞治: 並列コンピュータ工学, 昭晃堂 (1996).
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Noda, H., et al.: The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture, IEEE J. Solid-State Circuits, Vol.42, pp. 182-192(2007).
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Noda, H., et al.: The circuits and robust design methodology of the massively parallel processor based on the matrix architecture, IEEE J. Solid-State Circuits, Vol.42, pp. 804-812(2007).
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Mizumoto, K., et al.: A multi matrix-processor core architecture for real-time image processing Soc, A-SSCC, No.6-2, pp. 180-183(2007).
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溝上雄太, 中野光臣, 飯田全広, 末吉敏則: SIMD 型プロセッサMX コアにおけるPE間データ通信の高度化, 信学技法CPSY2007-64, Vol.107, No.415, pp. 19-24(2008).
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