Art

J-GLOBAL ID：201102213557713100   Reference number：11A1154916

A Genuine Power-Gatable Reconfigurable Logic Chip with FeRAM Cells

FeRAMセルを用いた本物の電力をゲート制御できる再構成可能なロジックチップ

Author (8)： IIDA Masahiro (Graduate School of Sci. and Technol., Kumamoto Univ.) ,  KOGA Masahiro (Graduate School of Sci. and Technol., Kumamoto Univ.) ,  INOUE Kazuki (Graduate School of Sci. and Technol., Kumamoto Univ.) ,  AMAGASAKI Motoki (Graduate School of Sci. and Technol., Kumamoto Univ.) ,  ICHIDA Yoshinobu (ROHM Co., Ltd.) ,  SAJI Mitsuro (ROHM Co., Ltd.) ,  IIDA Jun (ROHM Co., Ltd.) ,  SUEYOSHI Toshinori (Graduate School of Sci. and Technol., Kumamoto Univ.)
Material： IEICE Transactions on Electronics (Institute of Electronics, Information and Communication Engineers)  (IEICE Trans Electron (Inst Electron Inf Commun Eng))
Volume： E94-C  Issue： 4  Page： 548-556 (J-STAGE)  Publication year： 2011 
JST Material Number： L1370A  ISSN： 0916-8524  Document type： Article
Article type： 原著論文  Country of issue： Japan (JPN)  Language： ENGLISH (EN)

Thesaurus term： *ferroelectric random access memory ,  electric power control ,  possibility ,  logic element ,  memory (computer) ,  *nonvolatility ,  ferroelectrics ,  bistable circuit ,  volatile memory ,  *logic cell
Semi thesaurus term： flip-flop circuit ,  *logic cell ,  *reconfigurability ,  *power gating

JST classification (2)： Semiconductor integrated circuit  (NC03162T) ,  Power source circuit  (NC05060Q)

Reference (16)：

• USAMI, K. Methodologies for Power Gating. Leakage in Nanometer CMOS Technologies. 2006, 77-104
• KIM, K. Future memory technology including emerging new memories. Proc. 24th Int'l Conf. on Microelectronics, NIS, Serbia and Montenegro, 2008. 2008, 1, 377-384
• KIMURA, H. FeRAM and memory system. Int'l Solid-State Circuit Conf. (ISSCC) Supplymentary Material of SSD Memory Subsystem Innovation Forum, Feb. 2009. 2009
• AMAGASAKI, M. An embedded reconfigurable IP core with variable grain logic cell architecture. Int'l Journal of Reconfigurable Computing. 2008, 2008
• ROSE, J. Architecture of field-programmable gate arrays. Proc. IEEE. 1993, 81, 7, 1013-1028

Terms in the title (6)： FeRAM ,  セル ,  本物 ,  ゲート制御 ,  再構成 ,  ロジック