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J-GLOBAL ID:201102257963078090   Reference number:11A1900698

Coordinated Control of Shared Resources for Energy Efficient Chip Multiprocessors

共有資源の競合を考慮したチップマルチプロセッサ向け低消費電力化手法
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Material:
Volume: 2010  Issue:Page: ROMBUNNO.KONPYUTINGUSHISUTEMU,VOL.4,NO.2,40-58  Publication year: Apr. 15, 2011 
JST Material Number: L7379A  ISSN: 1882-7772  Document type: Article
Article type: 原著論文  Country of issue: Japan (JPN)  Language: JAPANESE (JA)
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Thesaurus term/Semi thesaurus term
Keywords indexed to the article.
All keywords is available on JDreamIII(charged).
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Category name(code) classified by JST.
Digital computer systems in general  ,  Computer system development 
Reference (28):
  • 1) Burd, T.D. and Brodersen, R.W.: Energy Efficient CMOS Microprocessor De-sign, HICSS '95: Proc. 28th Hawaii International Conference on System Sciences, pp.288-297 (1995).
  • 2) Chandrakasan, A.P., Sheng, S. and Brodersen, R.W.: Low-Power CMOS Digital Design, IEEE Journal of Solid-State Circuits, Vol.27, No.4, pp.473-484 (1992).
  • 3) Pering, T., Burd, T. and Brodersen, R.: The simulation and evaluation of dynamic voltage scaling algorithms, ISLPED '98: Proc. 1998 International Symposium on Low Power Electronics and Design, pp.76-81 (1998).
  • 4) Chandra, D., Guo, F., Kim, S. and Solihin, Y.: Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture, HPCA '05: Proc. 11th In-ternational Symposium on High Performance Computer Architecture, pp.340-351 (2005).
  • 5) Chang, J. and Sohi, G.S.: Cooperative Cache Partitioning for Chip Multipro-cessors, SC '07: Proc. 21st Annual International Conference on Supercomputing. pp.242-252 (2007).
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